General > General Technical Chat
An article on Static and Dynamic RAM.
Benta:
--- Quote from: Zoli on June 17, 2022, 07:53:09 pm ---Now, do you have anything to add to the SRAM vs. DRAM discussion?
--- End quote ---
No. Having seen other threads from the OP, not my thing.
Someone:
--- Quote from: Peter Taylor on June 17, 2022, 02:20:02 pm ---I am not given that option.
--- End quote ---
Well actually you are:
https://www.digitaltrends.com/computing/amd-teases-3d-v-cache-chip-performance/
huge globs of sram, that add very little to real world performance, which is why there isn't a market for consumer computers exclusively running on sram.
Build your own system! Intel offer you a choice of HBM DRAM or direct connect SRAM:
https://www.intel.com/content/www/us/en/products/details/fpga/agilex/i-series.html
https://www.intel.com/content/www/us/en/products/details/fpga/agilex/m-series.html
BrianHG:
In dram, each bank, for example: there are 8 of them in each DDR3 ram chip, has the entire column address space as static ram.
Proper interleaving the read/write access, if you operate in a forward or backward in a near sequential manner, other than the initial setup delay, your reads and writes should be at full clock speed, uninterrupted as if it were static ram.
Since CPU code hops all over the place, it takes smart compilers and coding techniques to attempt to maintain such continuous access which often fails. Large cache and branch prediction is designed to help overcome this. Video cards usually have architectures designed to help improve sequential access of dynamic ram.
Huge static ram as others here have said just ends up being slower due to layout and silicon area per bit size.
SiliconWizard:
Very fast SRAM above "small" sizes is also accessed synchronously in bursts anyway, having thus the same access constraints as DRAM. Just that they don't need refresh.
mawyatt:
--- Quote from: MK14 on June 17, 2022, 05:03:48 pm ---If I understand things correctly. The original IBM PCs (at some point), did actually have some kind of parity memory as standard, because of perceived bit-flip issues, with ancient technology DRAM chips of the time, where a theory of Alpha-radiation in the chip packaging (possibly cosmic-rays, as well), were/would cause a number of bit-flips.
--- End quote ---
Remember the issue was with the ceramic used in the memory package. Japan used Kyrocera ceramic packages and these showed no signs of "bit-flips", whereas all the US based suppliers used packages that had 3M ceramic and had "bit-flip" issues. Many folks jumped on the bandwagon saying US chip suppliers were inferior to Japan based upon this issue.
Intel found the source as slightly radioactive ceramic from 3M that caused the issue and instead of Intel keeping this to themselves and profiting, they let everyone know, including their competitors!!
Anyway, 3M cleaned up their ceramic and this issue was resolved.
Best,
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