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| Anybody Manufacturing Top Octave Synthesizers |
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| jonovid:
a top octave synthesizer ic is made up of 400 or more flip-flop's end-to-end to get all 12 notes from one clock input divided TOS chips require only one oscillator frequency, usually 1 MHz to 2 MHz. this high frequency signal supplies the clock frequency which is then divided by the TOS chips into the twelve equally tempered top octave musical notes of the scale. The twelve divisor ratios are multiples of the twelfth root of two which is 1.05946. used in 1960s retro combo organs and eurorack modular retro synthesizers but were do you buy them today? or is anybody manufacturing top octave synthesizer ic's http://www.armory.com/~rstevew/Public/SoundSynth/TopOctave/topdividers.html |
| retiredfeline:
I remember those, but never used one myself. I could only afford resistors for my stylophone. :-DD I have wondered if it could be done with a MCU. A search shows that somebody has indeed written firmware to do this: https://community.atmel.com/projects/emulate-top-octave-generator-ic-eg-mk50242 |
| Brumby:
--- Quote from: retiredfeline on December 19, 2021, 03:12:21 am ---I could only afford resistors for my stylophone. :-DD --- End quote --- Same. |
| Cerebus:
It would be trivial to do with even a small FPGA or CPLD, it's basically 12 off 10 bit counters. In fact it's so trivial that I've written (off the cuff) a 1 note version of it, building it out to the full octave is just cut and paste scut work. It synthesises to 18 LCs on a lattice iCE40, so would be 12*18 LCs = 216 LCs which puts it into the territory where the smallest devices made would accept the whole thing - it'd fit into a 256 LC MachXO2 which are only £3 a piece in 1 off quantities. Here's the Verilog code: --- Code: ---`timescale 1ns / 100ps module TopOctave ( input wire clk, input wire reset, output reg C5 ); parameter C5_divider = 478; // 1st note, repeat 12 times for the others ======================================== reg [9:0] C5_counter; always @(posedge clk) begin if (reset) begin C5 <= 0; C5_counter <= (C5_divider - 1); // Probably being hit around the head with a fencepost here. // probably better to run at a much higher clock to minimise the off by one error end else if (C5_counter == 0) begin C5_counter <= (C5_divider - 1); C5 <= ~C5; end else C5_counter <= C5_counter - 1; end // ================================================================================= endmodule `ifndef SYNTHESIS module TestBench(); parameter clock_period = 250, // 4MHz clock clock_pulse_width = clock_period/2; reg clk; reg reset; always #(clock_pulse_width) clk = ~clk; initial begin $dumpfile ("TopOctave.lxt"); $dumpvars (0, TestBench); clk = 0; reset = 0; #(clock_period) reset = 1; #(clock_period) reset = 0; #10000000 $finish; // 10ms end wire C5; TopOctave DUT (clk, reset, C5); endmodule `endif --- End code --- |
| Synthtech:
Flatkeys in England manufacture TOG modules as well as octave dividends for a lot of vintage organs and synths. A few of them even use FPGAs. |
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