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Are SuperCaps on 100-amp VCore supplies a thing yet?

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T3sl4co1l:
And again -- you aren't storing energy in this sort of application, you're just presenting a very low impedance to the load.  All those extra uF's are dead weight.  Electrically speaking, it's not strictly worse to have extra capacitance -- but if there's a cheaper, smaller method, why wouldn't you use it?

Tim

nctnico:

--- Quote from: frogblender on February 19, 2021, 08:15:15 pm ---I have a product which has a 300-amp VCore supply at .7v
(Yes, the asic it is attached to is fully capable of sinking battleships and setting your lab on fire).

The asic has very spiky current draw - which I figger easily exceeds the 300A supply, for usecs at a time.
Despite the underside of the asic being wall-to-wall with ceramic caps, there is still voltage droop during the current spikes (tens of millivolts, for a couple of microseconds until the switchmode turns on the jets.  But then once the current spike is over, the voltage will overshoot by the same amount).

--- End quote ---
Sound to me like there is a control loop problem or the control loop just can't keep up. I assume your DC-DC converter is using 3 or more phases? How much capacitance is at the output of the power supply if you only count the ceramic caps? An easy fix may be to add several hundred uf using MLCC capacitors in a small case. Something like 47uf 6.3V X5R 0603. As others pointed out electrolytics or even tantalum won't do you any good.

Based on the current & ripple you see in the original circuit you should be able to work out the extra capacitance needed from the maximum allowable ripple.

Siwastaja:
I don't believe the story of an ASIC taking 300A "peaks" for µsecs. Is this is digital ASIC? What are the clock frequencies of the most power hungry clock domains? For example, at f_clk = 100 MHz period is 10ns and dynamic/shootthrough current spikes would be shorter than this, in picosecond range, at least 5-6 orders of magnitude from being µsecs.

AFAIK, in a normally designed ASIC non-switching gates provide the capacitance required to drive capacitive load of the switching gates.

So assuming a digital ASIC running at today's clock speeds, if it is taking some power at µsec scale then this is more like the average power during some operation when many gates are switching many times, well 300A is of course possible but being average not peak power, this isn't a problem of capacitance. Just design a high-frequency converter, fill the underside of the board with MLCCs as usual, and off you go.

This sounds like approx. three times bigger than the typical desktop computer CPU Vcore supply, it shouldn't require any different approach. I bet the chip is larger, too.

A lot of phases, maximized f_sw, maybe GaN would help?

Capacitors need enough energy storage for the timescale defined by the f_sw and inductor value. The value may be surprisingly small, like some tens of uF, easy to achieve with bank of cheap 0201..0603 parts under the chip! After this is satisfied, all that matters is ESL and ESR.

Seeing overshoot mentioned, I agree it's likely a control loop issue.

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