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ASM programming is FASCINATING!

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Ian.M:
The enhanced baseline core kept RETLW (opcode 0x8nn).   The only difference  between enhanced baseline RETURN (opcode 0x01E) and RETFIE (opcode 0x01F) is one bit, which is needed for the instruction decoder to determine whether or not to set the GIE flag (to re-enable interrupts on RETFIE) and restore normal context.   The 'classic' baseline core doesn't use any 0x01n opcodes.

KL27x:
Musta added the edit to my post while you were typing.

I'm sure some of the PICs I have used had no automatic context saving. Your ISR had to start by saving context (w, page, bank, STAT?), then restore that stuff before you retfie. The PIC templates included that for you; you have to leave it there to assemble (if you are using interrupts and want it to work).

And they could technically have done the same with the GIE enable? Re-enable before retfie? Curious... Because now, you don't need separate retfie/return, do you? Or what else am I missing? :-//

... I suppose GIE bit would have to be globally accessible from all banks, if it must actually be the very last instruction before retfie, and maybe they couldn't use it or didn't have any more bits available, or I'm missing something more basic... hmm. reenable, interrupt before retfie executes, potential stack overflow?

Sorry for the digression. To the OP, especially, lol. And this is why threads go on for pages with nothing to do with the OP.

Ian.M:
Reenabling GIE would have to be deferred till after the next RETURN if you did it that way.  I suspect that it would be simplest to update GIE when the next NOP is executed as RETURN 'NOP's out the following instruction in the pipeline while its restoring the PC from the stack.   Therefore in your main code you'd BSF or BCF GIE followed by a NOP to action it.  Active skips and GOTO also 'NOP' out the following instruction so they'd have to be avoided between setting GIE and the ISR RETURN.

A bigger issue that made automatic context saving unavoidable was the choice forced on them by the lack of memory mapped SFR space (they'd already reduced the unbanked GPR space to only four bytes), to use a non-memory-mapped bank select register, so you couldn't read it back for context saving.

KL27x:
I think I understand why, now. But what's really amazing is that you know such minute details, at all!? Incredible.

I suppose that's where the "e" comes from.  RETurn From Interrupt.... and reEnable. 

KL27x:

--- Quote from: Ian.M on August 02, 2020, 08:37:11 am ---The enhanced baseline core kept RETLW (opcode 0x8nn).   The only difference  between enhanced baseline RETURN (opcode 0x01E) and RETFIE (opcode 0x01F) is one bit, which is needed for the instruction decoder to determine whether or not to set the GIE flag (to re-enable interrupts on RETFIE) and restore normal context.   The 'classic' baseline core doesn't use any 0x01n opcodes.

--- End quote ---

I chewed on that. So that extra bit doesn't even get processed in the normal cycle. Because all 12 bits of address space are already used. So it only gets checked in the last branch of the core machinery which does the new return-that-conserves-w-register instruction plus or minus the GIE enable, after. I feel like I'm one step closer to understanding the flow chart thing depicting the hardware structure in the datasheets. In the beginning, I thought that day would never come, but now I'm not 100% sure it won't, some day. (And if I don't, it WILL be for lack of trying; I don't know why I'm even thinking about it.  ???)

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