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ASM programming is FASCINATING!
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T3sl4co1l:
Right, with a single bus, you don't have the hardware advantage.  You might call such a system a "virtual Harvard architecture".

With modern machines, low level buses are very wide, and they don't care what data are being moved about; ultimately it gets into the caches it needs to, and those serve as a physical barrier again.

Tim
MK14:

--- Quote from: T3sl4co1l on July 30, 2020, 10:35:14 pm ---Right, with a single bus, you don't have the hardware advantage.  You might call such a system a "virtual Harvard architecture".

With modern machines, low level buses are very wide, and they don't care what data are being moved about; ultimately it gets into the caches it needs to, and those serve as a physical barrier again.

Tim

--- End quote ---

Yes, agreed.
SiliconWizard:
Just a side thought - sorry if it has been mentioned already - but many modern CPUs (even small MCUs these days) have some form of cache, and quite often separate cache for data and instructions. So even if it has a single address space for code and data like in a typical Von Neumann architecture, from the CPU's execution unit POV, it actually has two separate buses for code and data. This has obvious performance benefits, but also has some security implications.

Likewise, quite a few processor architectures these days are fundamentally Harvard but with some additional bridges allowing them to essentially be used as Von Neumann ones from a user's POV.

Berni:

--- Quote from: SiliconWizard on July 31, 2020, 03:19:37 pm ---Just a side thought - sorry if it has been mentioned already - but many modern CPUs (even small MCUs these days) have some form of cache, and quite often separate cache for data and instructions. So even if it has a single address space for code and data like in a typical Von Neumann architecture, from the CPU's execution unit POV, it actually has two separate buses for code and data. This has obvious performance benefits, but also has some security implications.

Likewise, quite a few processor architectures these days are fundamentally Harvard but with some additional bridges allowing them to essentially be used as Von Neumann ones from a user's POV.

--- End quote ---

The harward architecture is not just about having a separate instruction and data bus. Its actually about having a separate memory addressing space for instructions and data. You can have machine code at 0x100 in the program memory while 0x100 in data memory actually points to RAM instead. As a result of this a harward architecture CPU tends to have separate instructions for working with program or with data memory. Typically your usual MOV,ADD,XOR..etc instructions with addressing operands only work with data memory while there is a special instruction that loads a program memory location into a register.

This is what makes this architecture annoying for compilers since you can't just simply have a pointer to anywhere in memory. So this gives C compilers some oddities, like placing string constants into RAM so it can get a pointer to it, or introducing a special pointer type that works in program space instead.

If you go down deep enough then pretty much every CPU splits its bus into data and instruction somewhere. At some point there is a bus feeding the instruction decoder where only instruction data is fed in. It just so happens to join the main bus very early trough some latch that is only activated when an instruction comes along on the multiplexed instruction+data main bus. So an instruction cache is just simply placed in a convenient spot where only instructions flow trough so that the cache can be optimized for the access patterns that instructions use(or take hints from a branch predictor)
T3sl4co1l:
Ironically, x86 has a Harvard architecture IO bus -- multiplexed on the same main bus, but accessed in the instruction set by two special instructions (IN and OUT, and their later extensions for word width and repeat (string) access).  And a much smaller bus, too (not even the full 16 bits presented by the CPU, though, I forget how and where this was done on the PC-XT?).

PC IO ports haven't completely gone away of course, but by many orders of magnitude of data flow, memory mapped registers and data have decidedly won out. :)

Tim
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