Being trolled by STMicroelectronics

[tszaboo]

You know, I got a gotcha from ST sensors just now as well. LIS3xxx so the sensor has I2C and SPI interface. They are on the same pins. So far OK, I wouldnt care. How do you select between I2C and SPI? With the CS signal of the SPI.
Seriously, was this designed by aliens who never saw SPI in their life? So you want to use SPI, and connect more than one device on the same SPI line? Well, you better hope that the sensor doesn't interpret your SPI communication with a different device as a start condition on I2C, because then it starts sending data...

[rstofer]

Hey, Z80s in DIP40, PLCC44 and so on are still readily available (if nowhere near competitive with modern ARMs and such, let alone in terms of power).

Tim

I have a 50 MHz Z80 running CP/M off a Compact Flash drive.  It's pretty quick!  There are ARMs that are much faster but some of the jelly bean parts are in the same speed range.

The LPC2106 (ARM7TDMI) was only 60 MHz.

It's a fun board to play with when I get nostalgic.

[aandrew]

Seriously, was this designed by aliens who never saw SPI in their life? So you want to use SPI, and connect more than one device on the same SPI line? Well, you better hope that the sensor doesn't interpret your SPI communication with a different device as a start condition on I2C, because then it starts sending data...

Nothing wrong with this, and it is common with several vendors' devices. You're asking the vendor to do your systems level engineering which is impossible.

Now if you want to complain about I2C devices that *require* you to dummy-clock to get them out of being stuck in some goofy-ass state... ugh.

[T3sl4co1l]

And on that note...

There was an ADI part, a DDS I think, with SPI done by a retard.  Not even kidding.  Apparently the interface state does not reset on CS rising.  So everything is fine the first few frames, assuming you do everything perfectly, every time, of course.  Inevitably a bit error occurs, the whole thing goes out of whack, and you have no choice but to reset it.  There's no COMM reset, it's, I forget if it has a full-chip reset, or it needs to be power cycled.  But yeah, that.

Tim

[thm_w]

Low pass enable or Low power enable? The first one makes a bit more sense than the second, since you would expect it to work with low power = 0.

Also for general power down, ODR controls that so it seems to be unrelated. But its not that unusual for some chip to default to low power/disabled mode at startup.

[langwadt]

And on that note...

There was an ADI part, a DDS I think, with SPI done by a retard.  Not even kidding.  Apparently the interface state does not reset on CS rising.  So everything is fine the first few frames, assuming you do everything perfectly, every time, of course.  Inevitably a bit error occurs, the whole thing goes out of whack, and you have no choice but to reset it.  There's no COMM reset, it's, I forget if it has a full-chip reset, or it needs to be power cycled.  But yeah, that.

Tim

seems to usually happen when you let the analog designer do digital parts of a chip

[fourtytwo42]

seems to usually happen when you let the analog designer do digital parts of a chip

I worked for a company who's engineers designed an ASIC containing a very fancy modem for metropolitan area networks but the digital interface they put on it had less bandwidth than the modem!! Many many meetings were nececery to get them to accept that and from then on the knives were out...........

[AndyC_772]

Being trolled by STMicroelectronics engineers in the LIS2DE12 Accelerometer datasheet.

I think those accelerometers must have become part of the ST range via an acquisition.

Their data sheets are unrelentingly awful. Vague, incomplete, poor English, with a lot of relevant information located in separate "application notes" which, I strongly suspect, were written by (real) ST engineers after seeing just how bad the OEM data sheets were.

[Jeroen3]

The real ST-troll is in the ADC Injected channels. Now, this is a nice feature, don't get me wrong. It allows to "inject" slower (or faster) samplerate channels in a regular stream of triggered conversions.

But to configure it you have to assign a channel to the sequence registers: JSQ1 to JSQ4.
Good, you'd think it runs the sequence from 1 to 4.
No... It starts with 4-n count, thus with 2 injected conversions it does sequences JSQ3 then JSQ4.

Then, it stores the results in the injected data register, JDR1 to JDR4.
You'd think JSQ4 goes to JDR4.
No... The first conversion always goes to JDR1, thus with 2 injected conversion it does JSQ3=JDR1 -> JSQ4=JDR2.

This is some genius trolling to make sure you have to read all the fineprint.

Oh, and this is the best mistake not fixed for 19 revisions: attachment.

[tszaboo]

Seriously, was this designed by aliens who never saw SPI in their life? So you want to use SPI, and connect more than one device on the same SPI line? Well, you better hope that the sensor doesn't interpret your SPI communication with a different device as a start condition on I2C, because then it starts sending data...

Nothing wrong with this, and it is common with several vendors' devices. You're asking the vendor to do your systems level engineering which is impossible.

Now if you want to complain about I2C devices that *require* you to dummy-clock to get them out of being stuck in some goofy-ass state... ugh.

No, it would be fine, if you would have a 5th pin to select between SPI and I2C. Here, the CS pin of the SPI is this pin, which is ridiculous, because SPI cannot be shared with any other peripheral.

[Yansi]

The real ST-troll is in the ADC Injected channels. Now, this is a nice feature, don't get me wrong. It allows to "inject" slower (or faster) samplerate channels in a regular stream of triggered conversions.

But to configure it you have to assign a channel to the sequence registers: JSQ1 to JSQ4.
Good, you'd think it runs the sequence from 1 to 4.
No... It starts with 4-n count, thus with 2 injected conversions it does sequences JSQ3 then JSQ4.

Then, it stores the results in the injected data register, JDR1 to JDR4.
You'd think JSQ4 goes to JDR4.
No... The first conversion always goes to JDR1, thus with 2 injected conversion it does JSQ3=JDR1 -> JSQ4=JDR2.

The reference manual states clearly what is the order of the seqence, so what? 

[Red Squirrel]

For some reason this reminds me of when I found 12v LED bulbs on Amazon that use a normal 120v socket base.  It specified that they were 12v but there were so many reviews of people saying they blew up on first use.