Components you wish existed

[Druzyek]

Except for the 23 chips which run at 16MHz, and the 10 which run at 24MHz..

Except for 0 of those can run from FRAM at those speeds. Anything above 8MHz is wait stated, so only peripherals benefit from speeds higher than that.

[magetoo]

i take it you are on a MAC then ?

BSD.

All the FPGa tools are winodws / linux.

Well, yeah.  That's why I said I want open source.

Open source that wraps some secret sauce library if it has to be that way, but there's no reason for tools that just massage data to be locked to specific platforms.

[T3sl4co1l]

I have missed many times having current limited microcontroller pins, essentially for LEDs, but not only. Something like 1mA resolution up to 32mA. On all (GPIO) micro pins.

Hmm, interesting thought.  In regards to FPGAs, the pin drivers are selectable -- though I don't know offhand that any offer such a wide range, and that's by configuration, not user control.

It's something of a special-purpose and not-very-useful feature, which is why you probably won't see it any time soon...

The output stages wouldn't take up too much extra space -- a 20mA pin already needs a pair of 20mA transistors, whereas a variable stage only needs a binary series of transistors of the same total area.  It would take extra drive circuitry to get a usefully constant current, but that can be a relatively small blob of analog stuff (assuming the designers know what they're doing, and the CMOS process is capable of doing it well enough).  Big pain is, you'd have to route data and address buses all the way around the periphery of the chip, to set the drive strength registers.  Or have those embedded with the rest of the IO registers, but send all the individual bits around to each port pin.  Either way, the logistics are messy -- possibly worse than the need for pins at all!

Hmm, if you combined that with extended voltage range, or buffering, or something, you could have pins directly compatible with an even more diverse number of standards: e.g., LVDS (+/-8mA current mode; complementary in pairs), RS232 (+/- 6V or more, 20mA limited; single pins), RS422/485 (2-5V, 50-100mA limited; complementary), etc.  Optional would be ESD resistance on such pins, but the user can always add that externally.

Would also be neat to have analog input thresholds for all pins, either against one reference voltage (internally or externally programmed), or by bank or port, or even per pin.  That wouldn't need too much more analog stuff, since a dumb LVDS input stage sort of thing could be used -- keeping good performance and relatively tight voltage thresholds.  FPGAs have this sort of thing, when they have to support SSTL (SDRAM signaling) standards -- think LVDS, but a whole bus worth of "+" lines, with all the "-" brought into one VREF pin.  There would no longer be any need for a stupid "analog comparator" element in the chip -- any pin could serve the job, and with much better speed than normal.  What's typical of these things is bad offset voltage -- LVDS receivers are only guaranteed within 100mV, but they're usually better than that, and they can be calibrated.  You could build yourself a self-calibrating ADC with this, for example.

Tim

[David Hess]

Modern IC processes used for FPGAs and other high performance logic are not going to be suitable for general purpose programmable outputs.

Drive strength for instance applies to saturated operation (except for current mode outputs) and is for controlling transmission line effects.  Output voltage ranges are very limited unless a much more expensive IC process is used and even then, they are still limited.

RS-232 and RS-422/485 signal levels are not going to be possible and even 5 volt logic families usually used external level translation for them.  USB signal levels will also be difficult for an advanced process.

[T3sl4co1l]

Modern IC processes used for FPGAs and other high performance logic are not going to be suitable for general purpose programmable outputs.

Could you explain?

I wouldn't think FPGA processes would be all that applicable to MCUs, which I guess are usually 3.3V through and through.  Then again, there are plenty available in the >100MHz class with that sort of architecture (~1V core, bank IO), so it depends what you're referring to I guess.

Ultimately I should suppose the highest-falootin' FPGAs are very similar to the highest-falootin' processors, but those are all GTL or whatever, which I expect isn't far from the stuff the core is made of.  But yeah, that's all special fancy low voltage stuff, hardly the crusty high voltage stuff we like for embedded.

Drive strength for instance applies to saturated operation (except for current mode outputs) and is for controlling transmission line effects.

Isn't that the same thing?

Usually what's done for a CMOS current sink/source is, either just running it flat out -- you get a lot of resistance near the rail, but eventually it comes out of the resistive range and becomes constant-ish current.  This usually takes more than half the supply voltage, so it's not exactly useful.  But that already helps "transmission line effects", where it goes up a little bit right away, then even more slowly as the TL charges.  Instead of jamming it over and causing big bounce, or whatever.

A real current limited output should drop the gate voltage a little, usually as a current mirror.  Which could be switched on and off, but that might be slow; or cascoded, which would take a lot more area (the CCS will already have to be bigger to get the same Rds(on) or equivalent at the reduced Vgs, plus the switch).

So it really shouldn't be too big of a deal, but it would take more area, and a lot more nuts and bolts to make it useful.  Should be the same on any process, just scaled by the volts/amps of whatever is typical of it..

Output voltage ranges are very limited unless a much more expensive IC process is used and even then, they are still limited.

Well, you put it in a 3.3V IO bank and get 3.3V ranges, or etc.  Typical of FPGAs, at least the non-high-falootin' ones.  I haven't even checked if the fanciest ones have 3.3V banks or not.. wouldn't be surprised if they don't, at least on the high speed banks or whatever.

Having a high voltage bank would definitely be hard work in most processes.  Like a 15V (or even +/-15V) section among 3.3V (or lower) logic.  The transistors would also be massive, probably easily bigger than the rest of a chip that size (referring to like 250nm scale processes).

Out of, like, a 5V chip (most ATMega/PIC stuff people dick around with..), it needn't be much harder than the rest.

Tim

[David Hess]

Modern IC processes used for FPGAs and other high performance logic are not going to be suitable for general purpose programmable outputs.

Could you explain?

I wouldn't think FPGA processes would be all that applicable to MCUs, which I guess are usually 3.3V through and through.  Then again, there are plenty available in the >100MHz class with that sort of architecture (~1V core, bank IO), so it depends what you're referring to I guess.

Ultimately I should suppose the highest-falootin' FPGAs are very similar to the highest-falootin' processors, but those are all GTL or whatever, which I expect isn't far from the stuff the core is made of.  But yeah, that's all special fancy low voltage stuff, hardly the crusty high voltage stuff we like for embedded.

I am not saying that it is a problem of economics and not what can actually be done.  As you make the IC process more complicated it takes longer to make them and yields are poorer.  Any extra features have to be economical even for the applications which do not use them.

There is also a strong motivation to use a high volume process instead of a specialized low volume one.

Drive strength for instance applies to saturated operation (except for current mode outputs) and is for controlling transmission line effects.

Isn't that the same thing?

I am not exactly sure how this is done with CMOS outputs but the result is that the output impedance varies with voltage so the transition time is slowed by applying less current.  They want minimum delay and high drive but without hard switching which would cause excessive noise.

Usually what's done for a CMOS current sink/source is, either just running it flat out -- you get a lot of resistance near the rail, but eventually it comes out of the resistive range and becomes constant-ish current.  This usually takes more than half the supply voltage, so it's not exactly useful.  But that already helps "transmission line effects", where it goes up a little bit right away, then even more slowly as the TL charges.  Instead of jamming it over and causing big bounce, or whatever.

CMOS does not saturate the way bipolar does.  The channel resistance is still low when the output is near either rail so switching tends to be hard making ground and power bounce a real problem.  Bipolar output stages have a real advantage here.

A real current limited output should drop the gate voltage a little, usually as a current mirror.  Which could be switched on and off, but that might be slow; or cascoded, which would take a lot more area (the CCS will already have to be bigger to get the same Rds(on) or equivalent at the reduced Vgs, plus the switch).

So it really shouldn't be too big of a deal, but it would take more area, and a lot more nuts and bolts to make it useful.  Should be the same on any process, just scaled by the volts/amps of whatever is typical of it..

A complementary current mirror output (transconductance) could work but would need to be designed to operate in the linear instead of saturated region.  LVDS outputs use switched currents but not this type of output stage and have a limited voltage range at least according to their specifications but maybe that is an issue with their receivers.

Output voltage ranges are very limited unless a much more expensive IC process is used and even then, they are still limited.

Well, you put it in a 3.3V IO bank and get 3.3V ranges, or etc.  Typical of FPGAs, at least the non-high-falootin' ones.  I haven't even checked if the fanciest ones have 3.3V banks or not.. wouldn't be surprised if they don't, at least on the high speed banks or whatever.

Having a high voltage bank would definitely be hard work in most processes.  Like a 15V (or even +/-15V) section among 3.3V (or lower) logic.  The transistors would also be massive, probably easily bigger than the rest of a chip that size (referring to like 250nm scale processes).

Out of, like, a 5V chip (most ATMega/PIC stuff people dick around with..), it needn't be much harder than the rest.

For CMOS it is the gate oxide thickness and maybe diffusions and not the area and feature size that are the problem.  They already use multiple gate oxide thicknesses to support 3.3 volt I/O (and separate fast and low power core transistors) and adding more steps to support a rarely needed feature is going cost even for the applications that do not need it.

High performance microcontrollers separate their I/O and core voltages just like high performance gate arrays, microprocessors, and other logic.

[nuno]

Big pain is, you'd have to route data and address buses all the way around the periphery of the chip, to set the drive strength registers.  Or have those embedded with the rest of the IO registers, but send all the individual bits around to each port pin.  Either way, the logistics are messy -- possibly worse than the need for pins at all!

Or clock that data serially around the pins. Slow current level setting is ok as long as there's still fast ON/OFF control.
Or have current DACs in the core or wherever it makes more sense, route the single pin output to the periphery and multiply the current there.

Hmm, if you combined that with extended voltage range, or buffering, or something, you could have pins directly compatible with an even more diverse number of standards: e.g., LVDS (+/-8mA current mode; complementary in pairs), RS232 (+/- 6V or more, 20mA limited; single pins), RS422/485 (2-5V, 50-100mA limited; complementary), etc.  Optional would be ESD resistance on such pins, but the user can always add that externally.

We're talking microcontrollers here, so I don't see much use of LVDS and similar "high speed" related stuff - although RSxxx would be nice, although not my preference. I would like however, open drain/colector outputs capable of tolerating up to 15V on the pin when the transistor is off.

[Artlav]

A 100V, 3000F supercapacitor the size of BCAP3000.

But seriously:
-An FPGA-like device, but with analog cells - opamps, resistors, current sources, etc.
-Wider selection of bolt-mounted parts - diodes, mosfets, capacitors, etc. Not just high power, high price ones.
-More integrated power parts, like a MOSFET H-bridge with all the driving and level-shift circuitry already in it.

More wishful thinking:
-An MWIR/LWIR photodiode with high sensitivity/shunt resistance of silicon ones.

[Precipice]

But seriously:
-An FPGA-like device, but with analog cells - opamps, resistors, current sources, etc.

Check out Cypress PSOC. Sure, it comes with a free micro, but that's not the end of the world.
You may have to apply some careful thought to make it do what you want - there's no 'just copy a schematic in from a spice simulation', but it's proper analogue on a chip.

-More integrated power parts, like a MOSFET H-bridge with all the driving and level-shift circuitry already in it.

These exist, in various sizes - from SO8 to decent size power devices. What are you after?

[AdShea]

Actual Reverse-Blocking IGBTs that you can buy and aren't 3 generations behind.

GMR+Bias Magnet+Amplifier in a CSP for high-bandwidth current sensing.

Magnetic insulators (<1 mu materials) for actual flux barriers.

A wind-to-order service for standard bobbins/cores that doesn't require a trip to China and a MOQ of 1000s.

[coppice]

Except for the 23 chips which run at 16MHz, and the 10 which run at 24MHz..

Except for 0 of those can run from FRAM at those speeds. Anything above 8MHz is wait stated, so only peripherals benefit from speeds higher than that.

Those devices will incur wait states when running at full speed, but nothing like the quantity you imply. Configured correctly, changing the core clock from 8MHz to 16MHz to 24MHz gives substantial increases in execution speed. Perhaps you have tried them with the pipelining disabled.

Few modern MCUs run entirely free of wait states. Its rather inefficient to make them do so. Whether they use flash or FRAM, the non-volatile memory is generally the speed limiter. To get the best out of the silicon you need some measure of pipelining, caching or related tricks to hide that limitation. When the tricks run out you have to insert a wait state.

[coppice]

Electrolytics that don't dry up. Or a syringe to wet them again when they do.

Are you talking about really big electrolytics, because solid electrolytics can solve that problem over quite a wide range of sizes these days. They just cost a bit more.

[David Hess]

Electrolytics that don't dry up. Or a syringe to wet them again when they do.

Are you talking about really big electrolytics, because solid electrolytics can solve that problem over quite a wide range of sizes these days. They just cost a bit more.

The specifications for the solid electrolytic capacitors do not list operating lifetimes higher than high quality liquid electrolytic capacitors though.  I have not had any solid ones long enough to see what happens when they get old.

[coppice]

Electrolytics that don't dry up. Or a syringe to wet them again when they do.

Are you talking about really big electrolytics, because solid electrolytics can solve that problem over quite a wide range of sizes these days. They just cost a bit more.

The specifications for the solid electrolytic capacitors do not list operating lifetimes higher than high quality liquid electrolytic capacitors though.  I have not had any solid ones long enough to see what happens when they get old.

Most solids don't look that spectacular at maximum temperature. A wet electrolytic might be 1000 hours, and a solid might be 2000 hours at 105C. However, the lifetimes diverge considerably at more modest temperatures. Typically wets are rated for a doubled life with every 10C drop in temperature. Solids are rated for more than 3 times the life for every 10C drop in temperature. That doesn't sound a huge difference until you work it through. A 1000 hour/105C wet electrolytic has a life of 32000 hours at 55C (3 years). A 2000 hour/105C solid has a life of about 500,000 hours at 55C (50 years).

[kony]

But seriously:
-An FPGA-like device, but with analog cells - opamps, resistors, current sources, etc.

Ever heard of FPAAs ? http://www.anadigm.com/fpaa.asp

[coppice]

GMR+Bias Magnet+Amplifier in a CSP for high-bandwidth current sensing.

Magnetic insulators (<1 mu materials) for actual flux barriers.

Something like http://www.alpsgd.com/eng/product/current.html ?