Existence proof that Moore's Law continues to 7nm

[photon]

IBM first to 7nm! Intel must play catch up.

http://www.nytimes.com/2015/07/09/technology/ibm-announces-computer-chips-more-powerful-than-any-in-existence.html?_r=0

[photon]

Question: What in this photo is 7nm?

[T3sl4co1l]

Looks like there's thin white things between the towers (which are substrate, revealed by deep trench RIE and filled in around by SiO2 or something else), which might be the fins of the FETs?  Or gates?

AFAIK, feature size refers to the ability to go from "on" to "off" in any given layer, so there might not be any physical regions that actual size, but it's nonetheless required to make devices that small.

Tim

[photon]

I'm guessing the gate is as marked in yellow in the picture below and has length 7nm. The fin is the dark area that orthogonally intersects the gate. This is the channel between source and drain.

[photon]

The universe of leading edge fabs has been reduced to four: TSMC, INTEL, SAMSUNG and GLOBAL FOUNDRIES. With IBM's announcement (in the New York Times?) of working 7nm silicon, Moore's Law will extend from todays 14nm, to 10nm and 7nm. Will it go to 5nm? INTEL is no longer leading in process development. What happened? Why is IBM doing process development when they sold their fab to GLOBAL FOUNDRIES? Below an interesting article:

https://www.semiwiki.com/forum/content/4801-who-needs-lead-14-10-7nm-nodes.html

[Corporate666]

IBM first to 7nm! Intel must play catch up.

http://www.nytimes.com/2015/07/09/technology/ibm-announces-computer-chips-more-powerful-than-any-in-existence.html?_r=0

I thought Intel had 7nm working but were keeping their results very close to their chest?

It's an area I don't know much about at all - but I remember reading a year or so ago about the pathway to <10nm and it was known what they needed to do, but commercializing it cost effectively was difficult.

[photon]

Yes, I heard the same about < 10nm. I was thinking that 10nm, which is the next node scheduled for 2017, might be the last. With working silicon at 7nm, perhaps the 10nm barrier will be broken. With a 7nm fab to cost upwards of 8 billion, working silicon is the first step in getting someone to ante up that kind of money.

[Muxr]

I can't remember where I read it but it's not really 7nm  they are using some sort of equivalency to describe it. I think it's just an improved 14nm.

[photon]

I can't remember where I read it but it's not really 7nm  they are using some sort of equivalency to describe it. I think it's just an improved 14nm.

No, it is in fact 7nm.

[Muxr]

I can't remember where I read it but it's not really 7nm  they are using some sort of equivalency to describe it. I think it's just an improved 14nm.

No, it is in fact 7nm.

Ok I found it. Nothing on the chip is 7nm, it has a 30nm pitch. 7nm is just marketing. They have been doing this for awhile (calling the process with a made up name). It's still impressive, but it was about how the actual name of the process has nothing to do with the actual dimensions.

It originally used to refer to the width of a line + the space required between lines for the smallest conducting lines done on the process.
These days the number is mostly meaningless.

Source: https://www.reddit.com/r/hardware/comments/3cnkxm/ibm_unveils_worlds_first_7nm_chip/csxke8e

[photon]

I can't remember where I read it but it's not really 7nm  they are using some sort of equivalency to describe it. I think it's just an improved 14nm.

No, it is in fact 7nm.

Ok I found it. Nothing on the chip is 7nm, it has a 30nm pitch. 7nm is just marketing. They have been doing this for awhile (calling the process with a made up name). It's still impressive, but it was about how the actual name of the process has nothing to do with the actual dimensions.

It originally used to refer to the width of a line + the space required between lines for the smallest conducting lines done on the process.
These days the number is mostly meaningless.

Source: https://www.reddit.com/r/hardware/comments/3cnkxm/ibm_unveils_worlds_first_7nm_chip/csxke8e

I don't think reddit is the right source for semiconductor manufacture. None of the statements in the discussion in your post is correct. The dimension, 7nm, of a process always refers to the gate length of the smallest transistor you can make with the process. It does not refer to transistor pitch or line width. It's the yellow line in the image I posted above.

I agree that this number can be misleading. The real proof that a 7nm process node is better than a 10nm process node is that the number of transistors/area is doubled and power is halved. Otherwise it is just marketing bullshit.

BTW, no one will ante up $8 billion to fab marketing bullshit. The proof that the 7nm node is manufacturable only comes when it gets fab'd. Note that IBM did not claim a manufacturable process, so their silicon is not a proof of manufacturability but a proof of possibility. They have the first silicon to show that the node exists. It still has to be constructed.

[Howardlong]

I remember Sophie Wilson in one of the recent Youtube interviews describing it as, rather than transistor size (or possibly more correctly volume), it was more to do with density, in that some propellerheads have figured out how to fabricate them in on their sides, thus reducing area, providing the equivalence of a 7nm process if derived from transistor density based on a more traditional 2D process.

[Muxr]

I can't remember where I read it but it's not really 7nm  they are using some sort of equivalency to describe it. I think it's just an improved 14nm.

No, it is in fact 7nm.

Ok I found it. Nothing on the chip is 7nm, it has a 30nm pitch. 7nm is just marketing. They have been doing this for awhile (calling the process with a made up name). It's still impressive, but it was about how the actual name of the process has nothing to do with the actual dimensions.

It originally used to refer to the width of a line + the space required between lines for the smallest conducting lines done on the process.
These days the number is mostly meaningless.

Source: https://www.reddit.com/r/hardware/comments/3cnkxm/ibm_unveils_worlds_first_7nm_chip/csxke8e

I don't think reddit is the right source for semiconductor manufacture. None of the statements in the discussion in your post is correct. The dimension, 7nm, of a process always refers to the gate length of the smallest transistor you can make with the process. It does not refer to transistor pitch or line width. It's the yellow line in the image I posted above.

I agree that this number can be misleading. The real proof that a 7nm process node is better than a 10nm process node is that the number of transistors/area is doubled and power is halved. Otherwise it is just marketing bullshit.

BTW, no one will ante up $8 billion to fab marketing bullshit. The proof that the 7nm node is manufacturable only comes when it gets fab'd. Note that IBM did not claim a manufacturable process, so their silicon is not a proof of manufacturability but a proof of possibility. They have the first silicon to show that the node exists. It still has to be constructed.

That's just one source, every other source says the same thing, also I can't find anywhere where the process nm corresponds to any actual dimension. According to everything I read it's just a number the fab industry agrees on. Find me a source where it explains what 7nm, 14nm or 22nm for that matter actually means if you're so sure.

I only claimed that 7nm is just the name of the process and that it doesn't actually have any bearing as to the real dimensions found on the dies. It does have a relative bearing on the transistor density, just that the 7nm dimension is meaningless. Of course expensive fabs are not a sham. Who said that?

For instance top Quora answer on a similar question says the same thing:

These are the process sizes of transistors and are not actually the lengths and widths of the transistors themselves.. The smaller the size, the more transistors can be embedded to processor chip and the more computing volume available. The drawbacks are increased power usage and heat dissipation.

https://www.quora.com/In-microprocessors-what-does-32-45-and-22-nanometer-technology-mean-and-how-does-it-relate-to-efficiency-of-a-chip

I would be happy to be proven wrong though as I would like to know, I am just not convinced you know either. Have a source?

[Muxr]

I remember Sophie Wilson in one of the recent Youtube interviews describing it as, rather than transistor size (or possibly more correctly volume), it was more to do with density, in that some propellerheads have figured out how to fabricate them in on their sides, thus reducing area, providing the equivalence of a 7nm process if derived from transistor density based on a more traditional 2D process.

Yes, this is what I have found in my research. It's just a relative figure they [ITRS] came up with to name the process.

[miguelvp]

Intel is in 14nm for production (Altera Stratix 10 for example), but they are currently researching 10 nm and 7 nm fabrication.



Maybe IBM did leap them but Intel has been leading the rest for a while.



Also it's interesting to see that an IBM 10 nm is equivalent to an Intel 14 nm process.

Intel's 14nm process yields a 42 nm pitch, so to obtain a 30 nm pitch they only need a 10 nm process, and they actually announced over 5 months ago that they are going to abandon silicon for 7 nm and beyond, so that means that they are researching the 10 nm (30 nm pitch) using silicon.

[photon]

I can't remember where I read it but it's not really 7nm  they are using some sort of equivalency to describe it. I think it's just an improved 14nm.

No, it is in fact 7nm.

Ok I found it. Nothing on the chip is 7nm, it has a 30nm pitch. 7nm is just marketing. They have been doing this for awhile (calling the process with a made up name). It's still impressive, but it was about how the actual name of the process has nothing to do with the actual dimensions.

It originally used to refer to the width of a line + the space required between lines for the smallest conducting lines done on the process.
These days the number is mostly meaningless.

Source: https://www.reddit.com/r/hardware/comments/3cnkxm/ibm_unveils_worlds_first_7nm_chip/csxke8e

I don't think reddit is the right source for semiconductor manufacture. None of the statements in the discussion in your post is correct. The dimension, 7nm, of a process always refers to the gate length of the smallest transistor you can make with the process. It does not refer to transistor pitch or line width. It's the yellow line in the image I posted above.

I agree that this number can be misleading. The real proof that a 7nm process node is better than a 10nm process node is that the number of transistors/area is doubled and power is halved. Otherwise it is just marketing bullshit.

BTW, no one will ante up $8 billion to fab marketing bullshit. The proof that the 7nm node is manufacturable only comes when it gets fab'd. Note that IBM did not claim a manufacturable process, so their silicon is not a proof of manufacturability but a proof of possibility. They have the first silicon to show that the node exists. It still has to be constructed.

That's just one source, every other source says the same thing, also I can't find anywhere where the process nm corresponds to any actual dimension. According to everything I read it's just a number the fab industry agrees on. Find me a source where it explains what 7nm, 14nm or 22nm for that matter actually means if you're so sure.

I only claimed that 7nm is just the name of the process and that it doesn't actually have any bearing as to the real dimensions found on the dies. It does have a relative bearing on the transistor density, just that the 7nm dimension is meaningless. Of course expensive fabs are not a sham. Who said that?

For instance top Quora answer on a similar question says the same thing:

These are the process sizes of transistors and are not actually the lengths and widths of the transistors themselves.. The smaller the size, the more transistors can be embedded to processor chip and the more computing volume available. The drawbacks are increased power usage and heat dissipation.

https://www.quora.com/In-microprocessors-what-does-32-45-and-22-nanometer-technology-mean-and-how-does-it-relate-to-efficiency-of-a-chip

I would be happy to be proven wrong though as I would like to know, I am just not convinced you know either. Have a source?

I do have a source http://spectrum.ieee.org/semiconductors/devices/the-status-of-moores-law-its-complicated but unfortunately it proves you are right

However, the node number does mean something and is not marketing bullshit. As explained in this source, a new node must produce a doubling of the number of transistors per unit area. Since this requires a process shrink of 30%, the newest process node dimension is made 30% of the previous process node dimension. So, 10nm -> 7nm. 

[Muxr]

I was surprised that Intel got leaped to be honest. This is the first time in how long? IBM switched to silicon-germanium for this one.

[Muxr]

...

I do have a source http://spectrum.ieee.org/semiconductors/devices/the-status-of-moores-law-its-complicated but unfortunately it proves you are right

However, the node number does mean something and is not marketing bullshit. As explained in this source, a new node must produce a doubling of the number of transistors per unit area. Since this requires a process shrink of 30%, the newest process node dimension is made 30% of the previous process node dimension. So, 10nm -> 7nm.

Ok we agree. I was just stating it doesn't correspond to a real dimension. But yes it's still a good relative indicator.

[photon]

Interesting point of comparison. The lattice spacing of silicon crystal is 0.54nm. So, if you have a semiconductor feature size of 10nm, it can hold less than 20 silicon atoms. Running out of atoms is the reason Moore's Law will end for semiconductors.

[photon]

Here is an interesting article http://spectrum.ieee.org/semiconductors/design/the-highk-solution . It says that the dimension of a silicon atom in a silicon crystal is 0.26nm, about half of what I said above. It also details the herculean effort the chip industry made in going from 65nm to 45nm. Here doubling the transistor density was not the hard part but instead keeping the leakage current low and the drive strength high. I thought you might enjoy.

[photon]

Here are some nice photos of going 3D. http://www.eetimes.com/author.asp?section_id=36&doc_id=1327254
This will become more prevalent as Moore's Law ends. Maybe it's time to become a packaging engineer

[photon]

And what will replace semiconductors when Moore's Law runs its course. Time to study quantum mechanics.
http://www.eetimes.com/document.asp?doc_id=1327290

[tom66]

Won't die-stacking and 3D transistors become more common as performance increases are demanded?
Perhaps the next step in Moore's law is improvements in yield, making die-stacking more practical.

[donotdespisethesnake]

Intel says their 10nm process is delayed http://www.anandtech.com/show/9447/intel-10nm-and-kaby-lake

$8 billion for a fab - that ain't peanuts!

[photon]

Won't die-stacking and 3D transistors become more common as performance increases are demanded?
Perhaps the next step in Moore's law is improvements in yield, making die-stacking more practical.

The advantage of Moore's Law was that both transistor density (doubling the number of transistors) and power density (lowering the voltage) got better. Unfortunately, with die-stacking, only one gets better. Power density gets worse.

[photon]

Intel says their 10nm process is delayed http://www.anandtech.com/show/9447/intel-10nm-and-kaby-lake

$8 billion for a fab - that ain't peanuts!

10nm must be very hard! The IBM announcement of a 7nm test chip may have been more to hide a bad quarter than to announce a breakthrough. I don't think you can skip 10nm to go to 7nm. Too much to learn.

[eas]

Intel says their 10nm process is delayed http://www.anandtech.com/show/9447/intel-10nm-and-kaby-lake

$8 billion for a fab - that ain't peanuts!

The overall cost of the fab is one thing, the bigger issue for Intel these days is selling enough transistors to amortize it over. They've missed out on a lot of growth markets in the last 20 years. For a long time, the ongoing growth of the x86 market obscured those failures, but the desktop/laptop market is topping out, enterprise servers must be contracting due to virtualization, and Internet scale data centers have a lot more leverage since they tend to control their entire software stack. They still overwhelmingly choose Intel's chips, but Intel has to be careful.