Hardcore: PCIe spec missing timing of PERST to ActiveLink ??

[frogblender]

Attached (pg26 and 31 from pcie CEM) shows powerup for a system with PCIe devices.  I need to know what "4. Minimum PERST# inactive to PCI Express link out of electrical idle" is.   The spec doesn't state what the value should be, despite having all the other values.

Anybody know?

I have a plug-in card, with a dingbat-of-a-chip that requires a full 2 seconds after PERST to suckle it's firmware from an eeprom before it's ready for action...  I suspect this chip is busy suckling when the system bios enumerates pcie devices, and I miss the window of opportunity.

[dmills]

I don't have an official answer, but recall there being some discussion in one of the Xilinx PCIe IP block app notes where this can clearly be an issue. 

https://www.xilinx.com/support/documentation/application_notes/xapp883_Fast_Config_PCIe.pdf First paragraph says 100ms, but that appears to be derived from the minim length of TPVPREL (SEE UG517), so they are assuming that configuration starts as soon as the power comes good and must complete and be ready for link training and enumeration by the time PERST goes high.

Can you do a re enumeration once the OS is up?

Regards, Dan.

[frogblender]

I don't have an official answer, but recall there being some discussion in one of the Xilinx PCIe IP block app notes where this can clearly be an issue. 

https://www.xilinx.com/support/documentation/application_notes/xapp883_Fast_Config_PCIe.pdf First paragraph says 100ms, but that appears to be derived from the minim length of TPVPREL (SEE UG517), so they are assuming that configuration starts as soon as the power comes good and must complete and be ready for link training and enumeration by the time PERST goes high.

Can you do a re enumeration once the OS is up?

Regards, Dan.

Thanks Dan!   

PCIe base spec Rev1.1:  Sec 6.6: "A system must guarantee that all components intended to be software visible at boot time are ready to receive Configuration Requests within 100 ms of the end of Fundamental Reset at the Root Complex".  (where "fundamental reset" is PERST#).

Yes, we are working on getting OS-level rescanning working...

[dmills]

Note that I THINK the link training sequence has to fit into that 100ms because you kind of need the physical layer up before you can enumerate...

While I LIKE PCIe as a bus, this aspect of it can be a ball ache.

Regards, Dan.