How do >1GSa/s scopes get the samples into the SRAM fast enough?

[jeremy]

Hi all,

I have been playing with some high speed ADCs lately, but I have run across a barrier that I can't research my way around. The infamous Rigol DS1052E has 5-dual ADCs, so let's call it 10 ADCs. I understand that to run these you would need 10x 100MHz clocks, with 1/10th of 180 phase shift between them. But how do you get the data out of the digital side that fast?

I'm 99% sure that the Rigol does not have a >1GHz FPGA in it , and I noticed that all of the ADC digital outputs are fed to their own pins so there is definitely something parallel going on. I thought that maybe you could use 10x 16-bit high speed shift registers and then sample 80 bits of data at 100MHz, but I imagine there is a better way of doing it (and I don't think that is how it is normally done). Even if you had a fast enough FPGA, <1ns SRAM is crazy! (or at least to my feeble mind)

How is this normally done? I'm sure someone has already solved this problem, I just can't find it.

Any help would be much appreciated!

[Psi]

I cant say i fully understand how they work but I'm pretty sure the rigol chip is a custom design.

It may have a section of silicon that is clocked at 1ghz, separate to the core clock.
Probably just enough to capture and process the signal from all the DACs. After that it's likely a more reasonable 100mhz data rate with a guarantees that any <1ghz pulse was detected.

Either that or there are multiple sections running in parallel.
But i suspect there would still need to be a small section running at 1ghz.

[mikeselectricstuff]

When you run out of sequential speed you go parallel. This is why PC RAM is 128 bits wide. FPGAs are very good at this as you can create whatever datapath width you need.

[Psi]

Of course, that makes perfect sense now that i think about it.

[Rerouter]

but what about something like a 68000 cpu with no external ram chip? i have a DSO based on one able to do 100MSPS, yes the ADC's are custom asics but i have yet to work out how something running at 16Khz could process and display the data they spit out,

[tom66]

I don't own one, but doesn't the Rigol switch away from Long (i.e. 1 MB) memory if you use more than 500MSa/s? In short point memory the on chip FPGA memory is probably used, and you could load that in parallel probably...

[mikeselectricstuff]

but what about something like a 68000 cpu with no external ram chip? i have a DSO based on one able to do 100MSPS, yes the ADC's are custom asics but i have yet to work out how something running at 16Khz could process and display the data they spit out,

The CPU won't be involved in getting the data into memory - this will be done by hardware

[SeanB]

Yes, the CPU is probably handling things like the display, the keyboard and other housekeeping. The ADC is probably talking direct to a TI DSP chip doing the high speed work and providing the sample memory, the CPU only getting data at a much slower rate from the DSP internal memory.

[jeremy]

So even if you parallelise the ADCs, you still have the problem of having to store an 8bit sample every 1ns, as opposed to one big parallel sample every 10ns (which is much more doable) because the ADCs are necessarily out of sync. Unless the FPGA has 10 separate clock domains with individual external inputs (I can't work out if the Cyclones have this) of or can be clocked at higher than 1G, I can't see how this would work (but there is definitely a way, I'm trying to work out what that is!)

As for the Rigol, as far as I know it goes:

ADC -> Cyclone III FPGA -> Blackfin DSP

[EEVblog]

It's a little bit tricky, that is why not too many companies have developed 1GS/s scope front ends, Rigol were the first apart from the "big three" of Agilent, Tek, and Lecroy to do it (who all use custom silicon).
What Rigol almost certainly do is segment the internal FPGA SRAM into 10 blocks, each with it's own separate clock input. So each sample memory block records the data from each of the 10 ADC's at 100MHz, with the internal clocks in the FPGA working on the same staggered timing as the ADC's.
The real tricky part is getting all the internal FPGA timing and routing right, and I'm sure a lot of work went into that.
At the end of the acquisition period, the firmware reads out the data from all 10 blocks and puts the bits in the right order to reconstruct the data.
So it's using 10 separate clock domain inside the FPGA. So either the FPGA has to support that many, or they have hacked it somehow.
This approach can also work with external SRAM. I don't recall how many it has, but maybe it might use say 2 external SRAMs and you can use the same approach to get higher sample rate than the actual SRAM is capable of. e.g. 500Ms/s with 100MHz SRAM would need 5 external SRAMs

In fact you don't even need an FPGA to do this at all. You could simply clock the ADC data directly into 10 separate FIFO memory chips, all with that staggered clock scheme, and read the data out after sampling with any old processor.

Dave.

[jeremy]

Thanks Dave, makes sense.

In fact you don't even need an FPGA to do this at all. You could simply clock the ADC data directly into 10 separate FIFO memory chips, all with that staggered clock scheme, and read the data out after sampling with any old processor.

This was my original idea, I didn't think of skipping the FPGA though. 100MHz FIFOs are pretty expensive, I wonder if an FPGA or FIFO would be more cost effective?

[free_electron]

They make a system with an number of registers. Adc writes registers in cyclic fashin. First sample in reg 1, second sample in reg 2 , third inreg 3 etc...
Since they use more than one adc the interleave this as well. And then, like mike said they store it in parallel memory, like 32 or 64 bits wide. If you have 64 bit wide memory ,your memory runs at only 1/8 the sampling speed...
Fpga's have pll's on board that can make phase skewed clocks. Put a post divider and you can have staggered clocks. Easy to do. Use some fifo to biffer data while sdram refresh needs doing amd you are there.
Fpgas can be very fast internally. Prop delay inside is in the order of 410pS for a cyclone 3... Handoff through io is 5 to 7 nS... But as long as you stay inside you can go fast.
If you make a pipelined architecture you can 'ride the stream'.

[Rerouter]

ok, dug through the manual, and my unit does have 16 ram chips all fed directly off the ADC's, (2 channel 100MSPS for both) and all of them clocked at 25MHz with what i would assume would be phase offset logic, so back in the early 1980's, they did just use more ram chips