It's a little bit tricky, that is why not too many companies have developed 1GS/s scope front ends, Rigol were the first apart from the "big three" of Agilent, Tek, and Lecroy to do it (who all use custom silicon).
What Rigol almost certainly do is segment the internal FPGA SRAM into 10 blocks, each with it's own separate clock input. So each sample memory block records the data from each of the 10 ADC's at 100MHz, with the internal clocks in the FPGA working on the same staggered timing as the ADC's.
The real tricky part is getting all the internal FPGA timing and routing right, and I'm sure a lot of work went into that.
At the end of the acquisition period, the firmware reads out the data from all 10 blocks and puts the bits in the right order to reconstruct the data.
So it's using 10 separate clock domain inside the FPGA. So either the FPGA has to support that many, or they have hacked it somehow.
This approach can also work with external SRAM. I don't recall how many it has, but maybe it might use say 2 external SRAMs and you can use the same approach to get higher sample rate than the actual SRAM is capable of. e.g. 500Ms/s with 100MHz SRAM would need 5 external SRAMs
In fact you don't even need an FPGA to do this at all. You could simply clock the ADC data directly into 10 separate FIFO memory chips, all with that staggered clock scheme, and read the data out after sampling with any old processor.
Dave.