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How does doping go with the nanometer scale?
VinzC:
Hi all.
Maybe this question was partly answered in this board but I'm still curious as I haven't found the answer yet — probably out of laziness, I kindly plead guilty.
How do industries do doping if — correct me if I'm wrong — P or N doping is a matter of proportions such as 1 atom in 100,000 (strong doping) or 1 in 1,000,000 (normal doping)? How does that go with high integration scales where layers are made of only a few atoms?
Thanks in advance for your highlights.
Nominal Animal:
Consider this: in crystal silicon, the distance between nearest neighbors is 0.222 nanometers (0.222 nm = 2.22 Å = 222 pm).
The term "5 nm process" does not mean the features are on that size scale, it's just a label. It is better to look at transistor densities. One square millimeter is 1,000,000,000,000 square nanometers, and each square nanometer has about 6.78 silicon atoms on the surface of crystal silicon (FCC, or face-centered cubic lattice).
If we look at known transistor densities, let's consider the CLN5FF 5nm process by TSMC in 2019: 171,300,000 transistors per square millimeter. In surface area, we're therefore talking about 39580 surface atoms per transistor, or about 140×140 cells of the FCC lattice (which has an atom at each corner of a square face, and one in the center of that face, so two atoms per cell, on the surface of the lattice). That count only applies to the surface area, mind you; the structures also have depth, possibly hundreds of atoms deep, and at these scales we really need to look at the quantum mechanical model of the electron densities (a few outermost electrons only really interact, though), and cannot rely on macroscale rules of thumb like "current flows on the outer surface" at all.
The purpose of doping is to introduce vacancies (P-type, using acceptor dopants) or extra electrons (N-type, using donor dopants), and at these proportions, not to change the lattice properties otherwise.
Because we are very well within the quantum realm at these scales, the doped atoms do not really stand out that much from the lattice. (Actually, they do; the way they distort the lattice around them, depending on their own electron structure, is kind of a problem. But the reason for the doping, the extra electron, or the lack of an electron at that position in the lattice, really is "spread" pretty evenly over a large volume, not localized to that spot like one might think if they mentally visualize atoms as marbles or similar things. They're not, not at this scale.) In a very real sense, instead of that extra electron or electron vacancy being localized there, it really is shared within the lattice. If there was no distortion in the lattice otherwise, it would not matter much exactly where the dopants are, as long as they are not clustered together and were evenly distributed.
What does this mean, then?
It means that at this scale, we cannot design circuits like we do e.g. PCBs; it is more like building with LEGOs, and designing each LEGO (say, a FET, or a small high frequency conductor) using simulators modeling the actual electron-electron interactions using quantum mechanical models. These take a LOT of computing power to verify, especially because you really want to know if the block properties change depending on the doped atom location et cetera... but at the base of it, they are just invented by us humans, and then found via simulation and experiment to work well. The models – like how exactly is a FinFET constructed on a wafer – are well known in literature, but as far as I know, the exact practical details are Dark Magic Trade Secrets, known by all competitors, but not openly talked about.
The transistors are obviously the main building block – or at least the functional one –, but even "connecting wires" are similar building blocks at this scale. You don't just draw them willy-nilly as you like; they and their interaction with the other building blocks must be modeled and known. Essentially, nothing is "passive" at this scale. It has been this way for a few years now already. By shrinking the blocks, we need more functional blocks, and model them even more precisely, as the smaller scale will mean that only specific types of blocks will work together. For example, instead of a single FinFET "block" you use everywhere, you need a few different variants depending on what is around it and so on, and use the appropriate one for each – even though logically it is always the same "block". So, real-world engineering and physics work, to find out what works, both via simulation and practical experiments on wafers. Whether you consider that scientific or engineering research I can't say; to me, it's one and the same (and includes quantum chemistry, too) at this scale.
I myself am a molecular dynamics or computational materials physics toolmaker, trying to provide a next generation simulator for similar stuff – except that I don't work with the quantum mechanical models, but "classical" potential/force-field models, for examining non-electrical physical properties, like corrosion/radiation resistance and similar material properties. (Right now, all simulators really use programming techniques from the 1970s, and basically everybody is just throwing more hardware together to get shit done, instead of making the simulator software work better with the hardware we have. I'm that sort of a toolmaker: grumpy and unhappy about the waste of potential.) So, I have not done any of the kinds of simulations needed above myself, but I have supported users doing exactly that on VASP, Dalton, Gromacs, LAMMPS and other simulators; but even as a "glorified" programmer, my own core field is a bit different, on simulating the material properties in slightly larger systems (tens of thousands to billions of atoms – still less than a cubic millimeter of material –, but including things like how the doping process itself can be done, what is the penetration depth, damage to the crystalline structure, and so on).
Which means that if anyone with actual practical experience cares to post in this thread, that does trump my "theoretical"/simulation-based knowledge.
T3sl4co1l:
To add to that sense of scale in the stack-of-balls model -- an electron isn't pointlike, but rather smooshed out across, hundreds of atomic radii I think, depending on energy (wavenumber, whatever). Electrons in a crystal behave exactly like electromagnetic waves in a metamaterial, specifically a 3D lattice waveguide.
We even observe the same effects in an analogous EM structure: a transmission line or waveguide with periodic perturbations (alternating high and low impedance sections) gives a bandstop characteristic -- an electromagnetic bandgap (EBG). That is, EM waves are prohibited at certain wavelengths. So too, in a crystal, electrons are prohibited at certain wavenumbers.
And just as an EM wave is not a particle but the entirety of the field in the structure, so too, the electron is a field throughout the crystal. We identify particle-like properties under certain conditions, but those do not so much apply here.
So it's quite possible that charge carriers, thermally generated by the dopant atoms, wiggle about within the structure, making their presence felt pretty much wherever within the transistor.
Actually, we're at such small scales that, I think Debye shielding and thermal drift aren't very meaningful anymore? That is, below the mean free path of an electron bouncing around such a small bit of silicon*. Although maybe that isn't a meaningful point, as Debye length depends on doping (which is relatively strong here), and thermal drift may simply find charge carriers diffuse into (effectively, short circuited into -- recombined at) the connection terminals, in which case the concentration is simply the production rate from the dopants versus the sink rate by the terminals.
*And note that these are small discrete bits of silicon, indeed -- transistors are constructed on a die, then cut off from it using SOI (silicon on insulator) techniques. Usually something like, burying oxygen ions at a certain depth into the crystal, then annealing to form a buried layer of SiO2, insulating the transistors from the substrate. Which means the transistors are no longer metallurgically part of the same crystal, they still have the same orientation but do not touch it anymore.
On a tangential note, I wonder how many atoms of dopant are needed, before they precipitate as other compounds, out of such a tiny bit of silicon crystal?
Tim
David Hess:
--- Quote from: VinzC on June 03, 2021, 09:29:22 am ---How does that go with high integration scales where layers are made of only a few atoms?
--- End quote ---
As your question alludes to, poorly. The discrete nature of doping means that variation of the doping becomes greater as fewer atoms are involved. This creates an ultimate limit on feature size. As you might expect, compound semiconductors reach this limit earlier.
VinzC:
Well, thanks a lot for your elaborated response, guys. Just not sure I understand my own question now...
Maybe I should have narrowed it down to what I wanted to know exactly: a) are the advertised ratios — 1 in 1E5 for strong doping and 1 in 1E6 for normal doping — correct and b) are those ratios (roughly) conserved in high scale integration?
From what I've read above (thks Nominal Animal) that would be more like 1 "impurity" in 10,000 atoms minimum, right? So if that ratio makes sense, that's more than 2 orders of magnitude above normal doping, right? And we're only talking about the smallest "concentration", still with me?
So if the smallest "impurity" concentration is 100 times that of a normal doping, what's a strong doping like P+ or N+ then? Does that makes sense? Or is it the ratio between concentrations that matters? (I mean as long as strong doping is 10 times that of normal doping is okay... does that reasoning make sense?)
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