EEVblog Electronics Community Forum
General => General Technical Chat => Topic started by: gouthamec141 on December 16, 2014, 03:57:38 pm
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Recently I ran into this wonderful case study.
link : [http://www.quora.com/As-an-electrical-electronics-engineering-student-what-can-I-learn-right-now-in-just-10-minutes-that-could-be-useful-for-the-rest-of-my-life/answer/Arijit-Layek]
This is a small case study which discusses out of various implementations(2) for the same digital logic (4-input NAND gate). Basically I am looking for resources (technical papers/ books/ blogs/ ...... anything !!!) which throw some light on how should one choose a particular implementation from a choice of various designs for the same digital logic. The idea is that, one can expand their knowledge on digital logic design by studying these kind of case studies. I did a small research on the internet but couldn't find any relevant material (I may be wrong) so I decided to post this here. Any help is greatly appreciated.
Thanks in advance :-)
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Here's an example:
http://www.ti.com/lit/sg/sdyu001aa/sdyu001aa.pdf (http://www.ti.com/lit/sg/sdyu001aa/sdyu001aa.pdf)
The main tradeoffs are speed, operating voltage and output drive capability. Different families also have incompatible voltages or currents (in particular, ECL and CML types). Some are forward compatible (CMOS drives TTL) but not backward (TTL doesn't drive CMOS -- without special considerations, like extra pull-up current, or TTL-compatible inputs like the 74HCT series).
For general purpose work, you'll almost certainly be using 74HC or CD4000.
74HC is better than 7400 or 74LS TTL, runs on 2-5V, has good speed, and is very similar to the capabilities of pretty much any microcontroller out there.
CD4000 is ancient high voltage CMOS, so it's very handy when you need glue logic along with, say, a 12V analog circuit. Speed is slow (100s of ns) and output drive is weak (a few mA).
Many gate families are also available in alternate pinouts (compare some parts in the 74HC00 series to the 74HC4000 series -- which are, as you might guess, revised versions of select CD4000 parts), alternate polarities ('HC138 vs. '238), and alternate packaging (from 74HC1G04 single inverters to 74HC04 hex inverters to 8 and 16-wide bus inverters, and so on). You'll want to browse selection tables to see what parts are available and best suited to a given need.
As for implementations, more generally: anything more than a few chips is probably not worth implementing in discrete anymore. FPGAs (Field Programmable Gate Arrays -- globs of "make your own logic circuit") are so damn cheap nowadays, they're just as handy -- you do need a programmer and VHDL experience though.
Tim
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As for implementations, more generally: anything more than a few chips is probably not worth implementing in discrete anymore. FPGAs (Field Programmable Gate Arrays -- globs of "make your own logic circuit") are so damn cheap nowadays, they're just as handy -- you do need a programmer and VHDL experience though.
Also micro-controllers can be used for many things too, although they use serial, rather than parallel processing so are much slower for many tasks.
Often interfacing between logic circuit running at different voltages is a pain.
The CD4504 is good for interfacing between 3V to 5V and higher voltages up to 20V.
http://www.ti.com/lit/ds/symlink/cd4504b.pdf (http://www.ti.com/lit/ds/symlink/cd4504b.pdf)
The HCT series can convert between 3V and 5V.
I like the old CD4000 series purely because it has a wide operating voltage: all the way from 3V to 15V or 20V for the higher voltage variants. It's a shame you can't get MCUs with the same voltage rating as the old CD4000 series (ignoring those with a built-in regulator which have 5V input/outputs). I imagine it's just not possible to build flash memory with such a high voltage rating.
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First of all thanks for the instant replies. I should have mentioned this in my original post itself that I am not talking about actual hardware implementations, my post is related to digital design. I apologise for the confusion that I have created here. Anyway, the link I posted talks about various gate-level implementations of the same logic function. For example say a 4-input AND gate which can be implemented in the following ways :
(http://imgur.com/PgS8URe)
Both are logically correct but how to choose which is more optimal design ?
A slightly detailed answer is here
http://www.quora.com/As-an-electrical-electronics-engineering-student-what-can-I-learn-right-now-in-just-10-minutes-that-could-be-useful-for-the-rest-of-my-life/answer/Arijit-Layek (http://www.quora.com/As-an-electrical-electronics-engineering-student-what-can-I-learn-right-now-in-just-10-minutes-that-could-be-useful-for-the-rest-of-my-life/answer/Arijit-Layek)
Obviously delay and power dissipation are the benchmarks one should check for both of them but still I am looking for some resources which help me in expanding my view on how to choose between various available design alternatives ?
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Obviously delay and power dissipation are the benchmarks one should check for both of them but still I am looking for some resources which help me in expanding my view on how to choose between various available design alternatives ?
Choose the solution that ends up simpler. The synthesizers are pretty clever and are able to figure out a lot of stuff for you.
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The synthesizers are pretty clever and are able to figure out a lot of stuff for you.
yes I agree that EDA tools are way smart but I am in the learning curve now and I am looking for some benchmarks so that I can estimate the optimal design (at least for simple circuits) based on my requirements and constraints.
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As for implementations, more generally: anything more than a few chips is probably not worth implementing in discrete anymore. FPGAs (Field Programmable Gate Arrays -- globs of "make your own logic circuit") are so damn cheap nowadays, they're just as handy -- you do need a programmer and VHDL experience though.
You don't necessarily need to be able to programme VHDL (or Verilog). Quite a few tools allow the user to enter in schematic formats. The main reason I prefer VHDL is that if I need to change the chip in the future, it is easier to port the code.
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Between the two examples, the top one is generally better: propagation delays to all inputs are matched.
Input, output and gate count are all equal. Assuming AND gates are the simplest primitive in this case, there is no other optimal solution.
There may be some reasons to use the other, however: if the bottom most input is toggling quickly, it will incur the least power dissipation.
Transistor-level primitives are NAND and NOR, so you can save a few by shuffling around complements (de Morgan's theorem). Namely, using the top example, convert the first stage to NAND, and the second stage to NOR. Alternately, use a four-wide NAND and invert the output (the inversion often comes for free, since many logic families use buffered outputs).
Among programmable logic, it's likely neither of these circuits would be implemented directly as shown. CPLDs use large arrays, which at their heart, use many-wide AND gates to form products, followed by many-wide OR gates to form sums. FPGAs use look-up tables, as they call them, which are equivalent to smaller arrays; the difference is, with one latch per cell ("gate") and a smaller array, the cell density is much higher, so the complexity can be higher, as well as the number of states (allowing a more flexible design process, rather than lumping everything into one or a few bulky state machines).
I don't think there's any such thing as gate-level programmable logic available. ASICs most likely offer gate-level design, but you'll be sending your design through many FPGAs and simulators before getting to that stage! Otherwise, you'll be programming those discrete gates "with wire and solder", to quote the indomitable Pease.
Tim
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How to choose between various implementations for the same digital logic
Simple: pick the one that works best for you.
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With a string of glue logic one sometimes will implement another type of gate so one spare gate is available for use elsewhere.
A tool I have found handy in the past:
http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/10-gates/00-gates/chapter.html (http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/10-gates/00-gates/chapter.html)
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Between the two examples, the top one is generally better: propagation delays to all inputs are matched.
Input, output and gate count are all equal. Assuming AND gates are the simplest primitive in this case, there is no other optimal solution.
There may be some reasons to use the other, however: if the bottom most input is toggling quickly, it will incur the least power dissipation.
I am wondering how did you analyse both the circuit implementation just by looking at them. This is what the post was about, I want to know the sequence of your thought process. Given, some implementations for a given Boolean function, how should I proceed to decide the most optimal one. What resources would you recommend for a beginner ? Is it that one gains expertise by experimenting various circuits and then inferring from the results ?
Thanks a lot
Goutham
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With a string of glue logic one sometimes will implement another type of gate so one spare gate is available for use elsewhere.
A tool I have found handy in the past:
http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/10-gates/00-gates/chapter.html (http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/10-gates/00-gates/chapter.html)
Hey, this is really helpful :-+
Thanks,
Goutham
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With a string of glue logic one sometimes will implement another type of gate so one spare gate is available for use elsewhere.
A tool I have found handy in the past:
http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/10-gates/00-gates/chapter.html (http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/10-gates/00-gates/chapter.html)
Hey, this is really helpful :-+
Thanks,
Goutham
Yep, with a project nearly finished now it helped me choose an X-NOR :o it omitted several other gates and the X-NOR logic/truth table was perfect for what I needed.
Never used an X-NOR before....I was surprised to say the least.