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How to pronounce XOR...really?

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16bitanalogue:
I pronounce it as 'ZOR' because that is how I learned it from my professor in university and I know how it works. I even know the 'controversy' of how a multiple input XOR gate is supposed to function.
1. 1 and only 1 - output is HIGH
2. any odd inputs are high - output is HIGH

So a pox on all your delipidated ivory towers.  :blah:

JohnnyMalaria:

--- Quote from: 16bitanalogue on March 07, 2021, 12:25:01 am ---I pronounce it as 'ZOR' because that is how I learned it from my professor in university and I know how it works. I even know the 'controversy' of how a multiple input XOR gate is supposed to function.
1. 1 and only 1 - output is HIGH
2. any odd inputs are high - output is HIGH

So a pox on all your delipidated ivory towers.  :blah:

--- End quote ---

Ivory towers with fat removed?

JohnnyMalaria:

--- Quote from: 16bitanalogue on March 07, 2021, 12:25:01 am ---2. any odd inputs are high - output is HIGH

--- End quote ---

Well, that's just modern bullshit. I assume you are referring to cascaded XOR gates used for parity.

The X means EXCLUSIVE. One, not none, not more than one - One. Whoever first applied the term in the parity cases symbolizes the steady erosion of precise use of terminology that I see rampant in papers published by younger scientists. I suspect the same is true in T, E and (I hope not) M.

How old is your prof? I'd wager <35.

16bitanalogue:

--- Quote from: JohnnyMalaria on March 07, 2021, 01:03:58 am ---
--- Quote from: 16bitanalogue on March 07, 2021, 12:25:01 am ---2. any odd inputs are high - output is HIGH

--- End quote ---

Well, that's just modern bullshit. I assume you are referring to cascaded XOR gates used for parity.

The X means EXCLUSIVE. One, not none, not more than one - One. Whoever first applied the term in the parity cases symbolizes the steady erosion of precise use of terminology that I see rampant in papers published by younger scientists. I suspect the same is true in T, E and (I hope not) M.

How old is your prof? I'd wager <35.



--- End quote ---

You could walk through the binary arithmetic of a multi-input ZOR gate with examples of both interpretations, and even look up standard IEEE 91 - you know because this is an engineering forum.
Perhaps write an angry email to the creator of Logisim on why he allows for both interpretations.
Maybe write some Verilog code?

Or continue to rant and rave over "correct" language and pronunciations from your porch rocking chair because if those are different than your own then it means someone doesn't know electronics concepts.

The absurdity.  :-DD

MIS42N:
I vote for the parity interpretation. A collection of cascaded AND gates organised in any way such that there is a single output will produce a 1 output if all inputs are 1. A collection of OR gates are the same, will produce a 1 if any input is a 1. A collection of XOR gates produces a 1 with an odd number of inputs. No arrangement of XOR gates produces a 1 if and only if one input is a 1 and all others are zero. That would be quite involved.

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