Author Topic: What must one revise for interview for senior FPGA design engineer position?  (Read 900 times)

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Offline matrixofdynamism

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Different companies have different approaches. However, for those that have gone through the interview process enough times, they can certainly give their 2c. So my question is, what is the correct way to get prepared for a senior FPGA design engineer interview? What topics must one revise? Certainly knowing about adders and timing analysis is just the tip of the iceberge.
 

Offline Someone

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If its a senior role, then you should already know!
 

Offline tggzzz

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If its a senior role, then you should already know!

Beat me to it!

Revising is not useful. The OP should be able to demonstrate that they have used all the relevant techniques.

Having said that, revising for the general interview process and numbskull HR-droid questions can be valuable. Whenever I was in that position, I found I messed up the first few interviews - so I chose jobs that I wasn't reallty interested in.
There are lies, damned lies, statistics - and ADC/DAC specs.
Glider pilot's aphorism: "there is no substitute for span". Retort: "There is a substitute: skill+imagination. But you can buy span".
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Offline free_electron

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all you need to know is to always use the largest one with the fastest speed grade. you will exhaust its abilities no matter what.
all the rest is icing on the cake.
Professional Electron Wrangler.
Any comments, or points of view expressed, are my own and not endorsed , induced or compensated by my employer(s).
 

Online tom66

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You should probably know Verilog or VHDL :-) (which one is not really that vital, they are quite similar once you know one you can learn the other.)

If you don't know either of these, there's really no point in continuing...

If you do know HDL, then the chances are good you will know what types of questions will come up.
 

Offline mfro

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You should probably know Verilog or VHDL :-) (which one is not really that vital, they are quite similar once you know one you can learn the other.)

I would assume an applicant that first needs to learn the preferred implementation language doesn't really meet the new employer's requirements for a senior engineer :-DD .
Beethoven wrote his first symphony in C.
Nach oben
 

Online tom66

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I would assume an applicant that first needs to learn the preferred implementation language doesn't really meet the new employer's requirements for a senior engineer :-DD .

Well I am a senior FPGA & HW engineer and I only know Verilog (never had a need to learn VHDL so far) ... though, we only really use Verilog here so, I suppose it doesn't matter!
 

Offline SiliconWizard

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If its a senior role, then you should already know!

Ditto. Weird question for a senior position. That just makes it look at best like "FPGA design" is something the OP has done a long time ago, or not done enough that they would qualify for a senior position. But hey, what do we know. Now the mere idea of "brushing up" for an interview makes it look like a beginner's approach rather than a senior one.
 

Offline basinstreetdesign

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Ditto. Weird question for a senior position. That just makes it look at best like "FPGA design" is something the OP has done a long time ago, or not done enough that they would qualify for a senior position. But hey, what do we know. Now the mere idea of "brushing up" for an interview makes it look like a beginner's approach rather than a senior one.

Yes it is.  For me, having been through the FPGA wars when hand routing was the norm, I would only add that OP needs to be conversant with optimizing his options when entering the hardware design phase and when finalizing the design.

That is to say, choose the FPGA family which has a range of internal resources and speeds in the same footprint.  This, so that should speed become a limiting factor during timing analyses that the chip can be swapped out for a faster one after the proto is assembled and brought up.  Ditto if logic capacity becomes cramped during design.  Thus use the biggest/fastest mofo you can at first and then be able to downsize later to optimize size and cost.

If pennies/nickles becomes of paramount importance then you probably are working with the wrong technology to begin with...
STAND BACK!  I'm going to try SCIENCE!
 

Offline EPAIII

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A "senior" designer will almost certainly need to communicate with others in the company, both verbally and in writing. Your use of the word "revise" when something else is clearly intended, probably "review", immediately tells me that you do not have very much skill in that area.

This is a serious suggestion. I have been on both sides of the interview desk and can tell you that often a person's skill in the exact area of the job description is not always the reason for a job offer or for a polite letter to the opposite. If you are having trouble getting the jobs you want, I would suggest, in all seriousness, that you consider one or more courses in English composition.

And it would probably be a good idea to have an employment professional look at your resume.



Different companies have different approaches. However, for those that have gone through the interview process enough times, they can certainly give their 2c. So my question is, what is the correct way to get prepared for a senior FPGA design engineer interview? What topics must one revise? Certainly knowing about adders and timing analysis is just the tip of the iceberge.
« Last Edit: February 05, 2022, 08:00:53 am by EPAIII »
 

Offline EEVblog

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You "prepare" by bringing stuff to show.
In the case of FPGA, bring a laptop with your projects and code and be able to show and explain the tools.
But they'll probbaly ask about test benching, timing domain related stuff etc.
 


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