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| Is there a reason to avoid putting programming interface pins close? |
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| daqq:
So, I'm designing a PCB with a PSoC ARM with an SWD interface. The XRES pin is on another side of the package, some 16 pins away from the SWDIO and SWCLK pins, though close to the power pins, though there's the output of the internal 1.8V LDO in the way. Not cool. Then there's STM32 devices. I've worked with several and they always manage to fudge things up. The STM32F303VCTx has the NRST pin on the other side of the package as the SWD interface. The SWD interface, which is literally just two wires, is on two sides of a 4 sided package package and there are 3 signals between the two signals! What? I mean, what? Is there some reason that I'm not getting that makes it prohibitively expensive to put THREE PINS that will almost universally have one use case close to one another? I can understand that some large 40 pin interface interface will be all over the place since it needs to work on all kinds of packages and so forth, fair enough. But three pins. Come on! Really? Splitting three pins over three sides of the package (ignoring the need of the programmer to include +VCC and GND)? Really? I mean, I can work with that, sure, but it's a pain in the ass routing reset under half the package. I guess it's OK for mass produced devices that'll just have test points all over the place, but damn, for development and low volume stuff, really? Sorry, just pissed at finding out that this curse extends to yet another architecture. /rant |
| spudboy488:
I don't have an answer but the CPLDs I use have the JTAG pins scattered all of the device as well. |
| Berni:
The STM32 pinouts are made by a braindead monkey in general. They often do things like putting 3 pins of a SPI bus next to each other and then stick a clock pin like 20 or 30 pins away. Or give you a UART with RX and TX next to each other, yet the corresponding RTS and CTS are on the other side, yet the RTS and CTS lines of a different UART are right next by. I'm guessing some of those make sense on a BGA package, but then they just randomly distribute it into a TQFP in whatever order is easiest for the wire bonding machine. Or the chip designer doesn't even make consideration about it, placing bonding pads on the die wherever convenient, then the guy responsible for wirebonding it into a package just takes the easiest route. This becomes even more aparant when you try to connect very wide bus peripherals, like 24bit RGB video output or RAM with 16 data lines and 20 address lines. The lines are just scattered all the way around the chip, making PCB layout a living hell. You also get things like one pin having the TX pins of UART1, TX pins of UART2, RTS pins of UART3, SDA for I2C and MOSI for SPI all on one pin. But then there are things like GPIO pins where the only alternate function is a timer. Tho there is some reasoning behind that, they use the same silicon die to pack more peripherals into a smaller pin count package, even if you can't really make use of all of them since they overlap. Making it very infuriating that you want to add a feature to a product yet the peripheral you need for it is already barricaded in under other functions that you also need. |
| ataradov:
Reset is not totally necessary for programming. If it really gets in a way, you can always just drop it from the connector. |
| Siwastaja:
Similarly, the high-speed DCMI bus interface tends to be all over place, one of the bits or the clock on the opposite side of the package. I think ST scrambles the pinout on purpose. Why? No idea! Maybe a consultant thought it gives more weight to their design tools? Like, they design a good, normal pinout first, then randomize some 20% of it, leaving some level of sanity behind. |
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