So, I'm designing a PCB with a PSoC ARM with an SWD interface. The XRES pin is on another side of the package, some 16 pins away from the SWDIO and SWCLK pins, though close to the power pins, though there's the output of the internal 1.8V LDO in the way. Not cool.
Then there's STM32 devices. I've worked with several and they always manage to fudge things up. The STM32F303VCTx has the NRST pin on the other side of the package as the SWD interface. The SWD interface, which is literally just two wires, is on two sides of a 4 sided package package and there are 3 signals between the two signals! What?
I mean, what? Is there some reason that I'm not getting that makes it prohibitively expensive to put THREE PINS that will almost universally have one use case close to one another? I can understand that some large 40 pin interface interface will be all over the place since it needs to work on all kinds of packages and so forth, fair enough.
But three pins. Come on! Really? Splitting three pins over three sides of the package (ignoring the need of the programmer to include +VCC and GND)? Really?
I mean, I can work with that, sure, but it's a pain in the ass routing reset under half the package. I guess it's OK for mass produced devices that'll just have test points all over the place, but damn, for development and low volume stuff, really?
Sorry, just pissed at finding out that this curse extends to yet another architecture.
/rant