EEVblog Electronics Community Forum
General => General Technical Chat => Topic started by: tom66 on September 16, 2013, 11:10:02 pm
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I am repairing an LCD TV and this is the schematic I have to use.
Net names... everywhere! No obvious circuit flow. Inconsistent component positioning.
(The overall design of the power supply is absolutely terrible, but that's a topic for another day.)
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Looks fairly typical of the "new style" of schematics favored by newbies and idiots alike: Hey look, I don't have to put any thought into schematic layout if I just use this handy-dandy net name tool!
I'm only surprised it wasn't drawn in Eagle.
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When I first took a peek, I thought, "why did they format the .pdf so that it needs to be rotated 90 degrees?" But I quickly realized that rotating it 90 degrees doesn't improve anything.
The rules are: Inputs to the left, outputs to the right, voltage supply at the top, ground at the bottom, all text upright. There are occasional reasons to violate these rules, but the violations shouldn't be common, and you should always be able to state a reason for the departure from convention.
(The overall design of the power supply is absolutely terrible, but that's a topic for another day.)
I suspect the two facts that the schematic is bad and the design is bad might have something to do with one another.
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Wow, that's a bit "special". :)
Are 390R resistors going out of fashion? (It seems to use an awful lot).
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Hi,
Is this the manufacture`s original schematic?
It looks like the kind of schematic that you might make if you were reverse engineering something, until you have it all sorted out, then you would redraw it so that it was easy to read.
Jay_Diddy_B
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When it opens in my PDF viewer, it has this title:
S:/17-Tft/power/pw/17pw25/17pw25-4.cir
That seems like a file path on a network owned by a company that does lots of circuit designs. I'd say it is the original.
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they even made an 8 pin ic with the pin numbers going the wrong way :palm:
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It's a bit like the duplo of schematics. Bizarre how some symbols are enormous for no particular reason.
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All vestel chassis are crap.The schematic says Version 01 , for what ? ,version 1 of the schematic !
Theres a psu repair kit available,if yours needs repair.You can source the parts cheaper yourself and there might be some on ebay, havnt checked.
http://www.ohmsupplies.co.uk/REPAIR-KIT-POWER-SUPPLY-17PW25-4-BLOWN-Q935-R977-R97 (http://www.ohmsupplies.co.uk/REPAIR-KIT-POWER-SUPPLY-17PW25-4-BLOWN-Q935-R977-R97)
a note at bottom of page :
NOTE:- ALWAYS CHECK THE SMOOTHING CAP BEFORE SWITCHING ON.
NOT FOR THE17PW25-4 VERSION 3
same kit at chs :
http://www.chsinteractive.co.uk/electrical-components/spares-television-audio-video/television-spares/kits-repair-modification-and-upgrade/alba/repair-kit-17pw25-4-psu-alba-akai-schontech-techwood-telefunken-lcd32advd-lcd32880hdf-akfl3277h.htm (http://www.chsinteractive.co.uk/electrical-components/spares-television-audio-video/television-spares/kits-repair-modification-and-upgrade/alba/repair-kit-17pw25-4-psu-alba-akai-schontech-techwood-telefunken-lcd32advd-lcd32880hdf-akfl3277h.htm)
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It's a bit like the duplo of schematics. Bizarre how some symbols are enormous for no particular reason.
Like this?
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I don't have a copy of it unfortunitly, but no. That's not the worst schematic ever.
The worst schematic ever is one where the designer choose to make up their own symbols for every component and put a key table down the bottom showing what component each symbol means.
Actually, i guess the worst schematic ever would be the above without the key :-DD
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I've seen many schematics where there were wires drawn across symbols. Like wires connecting to pins from the inside of the symbol. Coincidentally, they were all drawn in Eagle. ::)
I have also seen schematics where the author refused to use the net naming tool, and instead made a nest of wires, which was impossible to decode.
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Most Lame:
(https://ultimachine.com/sites/default/files/images/arduinoMegaPololuSchem001.png)
Most Crowded:
(http://blog.iteadstudio.com/wp-content/uploads/image/2011_03/ds203-mini-dso-dso-quad-start-production-now_3.jpg)
Most Unconnected:
(http://www.rlocman.ru/i/Image/2011/10/17/Fig_3.gif)
If anyone's interested I can start a "Worst PCB EVER" topic which would be even more hilarious.
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Your Most Lame looks very Arduino. This "big glob of tiny subcircuits vomited onto the page and linked with net names" is the favorite schematic style of the Arduino crowd...
I don't think the Most Crowded is really all that bad, at least, from what I can see of the small picture. I'd rather break it into pages, but it is somewhat coherent.
Most Unconnected looks like something I drew up a while ago as a sarcastic example of Most Lame...
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Sometimes diagrams are hard to read because the author didn't use a big enough sheet size for the project (or split it into logical parts).
The "bunch of parts with a zillion nets" result is usually because they were too lazy to move the pins around on the parts with large numbers of pins.
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I've seen worse.
And have even created some bad ones myself because that was the "company standard" ::)
Altium was horrible for that. Most things had to be modular so it fitted with their reuse strategy, and demonstrated their harness technology etc.
So you'd end up with a 50 sheet schematic, with one page just for bypass caps etc.
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What's the standard for bypass caps? I usually put them right next to the supply pins of each individual IC, so you can easily see which cap belongs to which IC. I have often seen them put separately, like you just mentioned. Are there any written/unwritten rules that I'm not aware of?
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I'm kind of peeved by the MOSFETs that are in 6 pin packages and the schematic hardly makes it obvious that they're actually MOSFETs except for the G, S, D[1234] labeling.
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What's the standard for bypass caps? I usually put them right next to the supply pins of each individual IC, so you can easily see which cap belongs to which IC.
I try to put them on the schematic right next to the pins they bypass. That way I know I haven't left one out.
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What's the standard for bypass caps? I usually put them right next to the supply pins of each individual IC, so you can easily see which cap belongs to which IC. I have often seen them put separately, like you just mentioned. Are there any written/unwritten rules that I'm not aware of?
Unwritten rule is they go next to the chip or device to be bypassed, so the board layout person (even if they same person) knows where they go.
Not to do so rightfully leads to pubic humiliation from your peers.
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Most Crowded:
(http://blog.iteadstudio.com/wp-content/uploads/image/2011_03/ds203-mini-dso-dso-quad-start-production-now_3.jpg)
Scarily, I knew exactly what that diagram was. A few months ago I dissected and simulated the analogue input to see just how bad it's performance was. Despite being crowded it is at least quite readable. Unlike the increasing number of corporate engineers who insist on putting one IC per page. Aaargh!
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Your Most Lame looks very Arduino. This "big glob of tiny subcircuits vomited onto the page and linked with net names" is the favorite schematic style of the Arduino crowd...
I think the Arduino crowd copied that style from (professional) laptop schematics, which are all like that. Including putting bypass caps on their on page (http://img14.imageshack.us/img14/7240/u2yp.png), and all the ground pins together (http://img542.imageshack.us/img542/7227/kf2k.png)...
Then again, I can't think of any better way to show connections to a package with several hundred pins, although it's certainly a different situation than an Arduino and less than half a dozen parts.
What do you think of the Apollo AGC (http://klabs.org/history/ech/agc_schematics/) schematics?
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Your Most Lame looks very Arduino. This "big glob of tiny subcircuits vomited onto the page and linked with net names" is the favorite schematic style of the Arduino crowd...
Oh crap - I have some that look like "most lame". What's wrong with it? :D
Actually it's much more confusing than mine, but I am most definitely guilty of often not splitting things out into sheets when I should, or using net names to link different functional parts of a circuit.
On the other hand, my schematics look more like the ones in Cypress data sheets, so maybe I'm not that bad? :)
I find the Arduino crowd often has BS like a power and ground net that zig zags all over the schematic and connects to every power/ground pin.
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I think most of the time people wire it up quick and dirty with net names because they're short on time.
Expecting to come back later and lay it out properly, which never happens :P
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The worst drawn schematic I ever saw was in some TV equipment--can't remember the firm but it was a smallish Brit company.
The device circuit was drawn on two pages:
The first one was ok--Hand draughted,but quite readable.
The second page started off OK,but just in from the LHS, turned into a hand scribbled mess,which looked as if they caught the designer on his way out the door for his farewell sendoff.
It all tapered off in a tail at the RHS,where it was almost impossible to make out what symbols were intended.
Why they didn't get someone to sort it out before sending if off to the customers is beyond me!
It was a good piece of gear,too!
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I really hate these 'lego' schematics with no connections - the biggest annoyance is it's hard to tell how many nodes are connected to any given point.
Given that this laziness is now so widespread, something that would improve them is if next to the node name, it also showed how many other nodes were connected to that one. This could be done automatically by the tool. Another possible enhancement would be if the nodes had short lines pointing in the direction of each node it's connected to, to make it easier to find.
What's the standard for bypass caps? I usually put them right next to the supply pins of each individual IC, so you can easily see which cap belongs to which IC. I have often seen them put separately, like you just mentioned. Are there any written/unwritten rules that I'm not aware of?
That's something I don't care about as it doesn't affect the understanding fo the functionality.
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I am repairing an LCD TV and this is the schematic I have to use.
It's already a miracle you actually have a schematic. At work I even have trouble finding them for boards that were designed in-house...
Considering everything is throw-away these days I would only expect a list of part numbers for the individual boards
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I am repairing an LCD TV and this is the schematic I have to use.
It's already a miracle you actually have a schematic. At work I even have trouble finding them for boards that were designed in-house...
Considering everything is throw-away these days I would only expect a list of part numbers for the individual boards
That certainly doesn't look like a schematic for servicing, or for anything other than internal use during design. Never overestimate the security of Chinese corporate networks... or underestimate the tenacity of those who want to get schematics. ;)
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Vestel is a Turkish company that produce junk TVs, among other electronics. I acquired the schematic along with hundreds of others.
Looks like one of the five paralleled UF5402s has shorted, taking the MOSFET, PFC IC and ten other components with it. And to think -- Toshiba, Sharp and Hitachi -- formerly respectable brands -- are now re-badging this same Vestel chassis!
Ugh. At least the TV was free.
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Some schematics are auto drawn, there is a tool called Cadence system architect the allows you to connect nets in a spreadsheet and then it auto gens a schematic routed with net names only. It makes sense for digital net lists like TVs, PC motherboard and dimms but not so much for mixed signal designs.
I have to say that honestly I prefer to use net names because I hate trying to follow a line snaking around a page with 20 other nets adjacent and intersecting.
That "most crowded" schematic was ok organized in my opinion... Not a fan of flipping through endless pages of schematics just for gratuitous white space.
Analog and rf circuits flow much better so yes direct connections are preferred here.
I guess the one thing that is needed if you use net names is a proper crefer need to annotate names onto each dangle.
It is a matter of style and preference. At the end of the day, a logical flow is important and all good circuits have a logical flow...
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The OP schematic looks indeed like it was put together from small verified working snippets. I dont think it is that horrible. The worst I've seen was a bunch of jelly bean transistors, resistors 74 series IC dropped on one page all connected together without proper description and logical order. Even the connectors' functions were not obvious.
The problem with the "most crowded" is basically the improper use of busses. I made more crowded A3 pages, but there was a logical way of the signaling, everything went from left to right, without crossing, each block labeled, and having proper symbols.
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I don't have a problem with the busses in the "most crowded". It's as graceful a way as any other to draw a large number of digital signals. My problem with net names is that I can't see everything that connects to a signal without reading every single net name on the whole diagram. At least with the bus, the digital signals are confined to a section.
Grouping digital signals IMHO is OK. I often use buses for things like SPI. It's not the "traditional" application, but really, very few circuits have parallel A/D buses anymore - might as well find a new application for the tool.
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My other pet hate is when the EE decides to use certain pins on the microcontroller because it makes drawing the schematic easier, even though it makes my life as software engineer harder. That's one reason why I like to be involved with the hardware design as much as possible, or just do it myself.
That's just lazy and dumb
Ideally the schematic software should allow you to quickly and easily easily move pins around on a symbol to make it neater - I'm not aware of any tools that allow you to do this, though I've not used many different ones.
A much better approach is to choose pins that make the PCB layout nicer (shorter traces, fewer vias, better EMC, maybe even fewer layers). Unfortunately tool support for determining pinouts at layout time (other than by back-annotating pin-swaps) isn't generally good IME.
This is why I usually do the PCB first & (maybe) the schematic afterwards, when all the details have been nailed down. Although some software allows for pin-swaps on things like equivalent gates (if the library has been set up right), It's just too hard to effectively express the constraints on MCU pin swappability, especially as these will depend on design details like which peripherals are used.
Software is easy to fix.
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I like Mike's idea of putting net connection counts right after the net name on the schematic. It'd make gauging fanouts easier. I'll admit, yeah, I do the "huge mess of random nets" thing with large FPGAs, swapping i/o to make the routing job easier.
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My other pet hate is when the EE decides to use certain pins on the microcontroller because it makes drawing the schematic easier, even though it makes my life as software engineer harder. That's one reason why I like to be involved with the hardware design as much as possible, or just do it myself.
I usually first connect it so it looks good on the schematic, then rearrange it so it's convenient to route the PCB and I later make modifications to optimize bit juggling in software.
Software does get the last word, as long as that doesn't cause a bigger inconvenience with the layout. :)
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So what exactly are the problems with the "Most Lame" example? Other than the fact that there is only one sheet (which if I had to guess was due to using the Lite version of Eagle which only allows one sheet per schematic).
The circuit seems to be divided up into functional areas. Sure some are really small (like the reset), but it seems consistent?
Just a young player looking out for traps.
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This is the worst schematic that I have ever seen. This one is made by the queen arduino herself. It even has overlapping parts and diagonal nets!
http://www.ladyada.net/media/wavebubble/cigpack-main%20rc1.pdf (http://www.ladyada.net/media/wavebubble/cigpack-main%20rc1.pdf)
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Most Crowded:
(http://blog.iteadstudio.com/wp-content/uploads/image/2011_03/ds203-mini-dso-dso-quad-start-production-now_3.jpg)
Scarily, I knew exactly what that diagram was. A few months ago I dissected and simulated the analogue input to see just how bad it's performance was. Despite being crowded it is at least quite readable. Unlike the increasing number of corporate engineers who insist on putting one IC per page. Aaargh!
This schematic looks fine to me. It looks very easy to read and compact. But why are there a kaggillion pins from the to ic's on the same buss? :wtf:
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My other pet hate is when the EE decides to use certain pins on the microcontroller because it makes drawing the schematic easier, even though it makes my life as software engineer harder. That's one reason why I like to be involved with the hardware design as much as possible, or just do it myself.
I had a boss, who makes software also, and lot of times he ordered us to modify hardware, just to make his life easier. Every now and than we had to put extra hardware on the board, just to make the software super fancy. We actually payed for this. Once I had to rename 2-3 times my signals on a 15+ page schematic, just because he changed them in the software, and I had hard time explaining him, that I cannot name the signal the same before and after a series termination resistor. I remember, once he tried to force me, to put an extra XOR gate on two signals coming out of an FPGA :scared: which was never used anywhere else. Total incompetence.
I don't wish to anyone to have the same experience.
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So what exactly are the problems with the "Most Lame" example?
Because of the acute netnameitis, you cannot tell by looking at one part of the schematic what else it connects to. If I'm trying to troubleshoot that circuit, I don't want to just see that there's a MOSFET gate switched by a signal E0-HEAT, I want to know what sources that signal and what else the signal goes to. The nice thing about a line is that you can trace it and see every single thing it touches.
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This is the worst schematic that I have ever seen. This one is made by the queen arduino herself. It even has overlapping parts and diagonal nets!
http://www.ladyada.net/media/wavebubble/cigpack-main%20rc1.pdf (http://www.ladyada.net/media/wavebubble/cigpack-main%20rc1.pdf)
You just provided an example for the crap I was referring to in one of my previous posts:
I've seen many schematics where there were wires drawn across symbols. Like wires connecting to pins from the inside of the symbol. Coincidentally, they were all drawn in Eagle. ::)
(https://www.eevblog.com/forum/chat/is-this-possibly-the-worst-drawn-schematic-ever/?action=dlattach;attach=60732)
Another thing that really ticks me off is text placed over connections, so you have trouble both reading that text and following a signal path. Again, same schematic. :palm:
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I work in a company that has been around for a long time. When they first started doing PCBs it was decided that the Drawing Office would lay them out as they had full drawing boards and were used to doing drawings without messing them up.
Fast forward 30 years and the mandate that "Drawing Office does the PCB artwork" morphs into "Mechanical Designers do the PCB layout". As a result, they also maintain the electronic symbols so what we get as a schematic symbol turns into a generic box with the legs around it - regardless of were the input / outputs are. Try complaining that it makes the schematic unreadable and they explain that as they don't understand the schematic they don't expect anyone else to.
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I've produced some poor schematics in my time. I'm quite a disorganised and messy person and when I first started schematics were drawn by hand. I could do a reasonable job to start with, but with a project that ran for four years extra blocks had to be added usually where there wasn't really room for them.
What's the standard for bypass caps? I usually put them right next to the supply pins of each individual IC, so you can easily see which cap belongs to which IC. I have often seen them put separately, like you just mentioned. Are there any written/unwritten rules that I'm not aware of?
Unwritten rule is they go next to the chip or device to be bypassed, so the board layout person (even if they same person) knows where they go.
Not to do so rightfully leads to pubic humiliation from your peers.
I believe that there's a European law against pubic humiliation.
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Ideally the schematic software should allow you to quickly and easily easily move pins around on a symbol to make it neater - I'm not aware of any tools that allow you to do this, though I've not used many different ones.
I move pins around on schematic symbols in Altium all the time, but mainly for micros. No need to go make a custom version of that symbol for that schematic. Just unlock the pins (for that part) and drag them wherever you want. So easy and can make a massive difference to the flow of a schematic.
Many many years ago I used to do the board layout then do the schematic. Way too easy to screw up imo. Now, even for simple projects I do the schematic first. Sometimes it starts out with just a few critical parts (connectors, transformer and other large parts). This is so I can get a feel for they board size and how the I/O will work out. Then I'll add more to the schematic, import the changes and continue the board design. Quite often the schematic changes according to the board space limitations.
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Yeah nets across a symbol makes me very in comfortable
Other that those few nets, not bad style in my opinion. I wonder if they went wonky when generating the PDF or a last minute drag of a symbol. Surely no one would do that consciously.
I think everyone's got it right, proper layout is first priority, software ease is second, schematic hygiene third. Although software needs to justify their request with an explanation that I like otherwise tough luck...
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...with one page just for bypass caps etc.
Hey, now. ;)
Where applicable, the bypass cap is on the IC. But some designs have more "dispersed" on the board. I add them so the layout gets them. I go back and delete what I don't feel is necessary. (I'm always the layout guy)
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This one's fun to troubleshoot from...
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Mother of God that is one horrid analog schematic. What is with these people who think schematic pages are expensive? |O
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Most Crowded:
(http://blog.iteadstudio.com/wp-content/uploads/image/2011_03/ds203-mini-dso-dso-quad-start-production-now_3.jpg)
Scarily, I knew exactly what that diagram was. A few months ago I dissected and simulated the analogue input to see just how bad it's performance was. Despite being crowded it is at least quite readable. Unlike the increasing number of corporate engineers who insist on putting one IC per page. Aaargh!
But that schematic is ALSO a schoolbook example of how NOT to draw schematics. they just had to cram everything on a 11x17 ...
split that sucker in an analog section and a digital section. a nice bus interconnects the two.
and for 'f#$% sake : make CUSTOM symbols to get rid of the wire spaghetti. make little block diagrams inside the ic symbols to show what is inside.
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Ideally the schematic software should allow you to quickly and easily easily move pins around on a symbol to make it neater - I'm not aware of any tools that allow you to do this
Altium. Since version 11.something. Simply double click a symbol, untick the 'lock pins' checkbox and you can move em around. you can even rename or renumber pins , i use this all the time
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Ideally the schematic software should allow you to quickly and easily easily move pins around on a symbol to make it neater - I'm not aware of any tools that allow you to do this
Altium. Since version 11.something. Simply double click a symbol, untick the 'lock pins' checkbox and you can move em around. you can even rename or renumber pins , i use this all the time
Wow, this is amazing
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All PCB packages need to have this. Dammit f_e, I'm usually perfectly happy to use KiCad, but every time you start describing Altium I need a napkin...
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Wow, this is amazing
Wait until you see AD 14 in a few weeks. That will be jaw dropping and eye popping .... We ( the silicon valley users group) got an overview last week at the Marriott hotel here. (with an excellent lunch buffet to boot).
It gets some capabilities that pushes Altium into a whole new category of PCB tools... yes, these are back to the core of schematic and PCB updates. They are getting serious ...
To paraphrase Dr. Brown : When this thing hits 88 miles an hour you are going to see some serious sh...
The first step has been taken in AD14 with a hint to the future : they have an Eagle importer (sch and brd) in AD14 ... and other importers are in the works... hint hint...
Early next year (target February) another big game changer is coming with the new pricing model... with a few 'entry levels' ... hint hint
And that's all i'm going to say about that. Go read that shareholder overview that was posted in a topic here a few weeks ago and connect the dots...
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Ideally the schematic software should allow you to quickly and easily easily move pins around on a symbol to make it neater - I'm not aware of any tools that allow you to do this
Altium. Since version 11.something. Simply double click a symbol, untick the 'lock pins' checkbox and you can move em around. you can even rename or renumber pins , i use this all the time
I just fired up DXP (AD 8.x) and that has it. DXP was probably where it was introduced. That's around 10 years ago!
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Mother of God that is one horrid analog schematic. What is with these people who think schematic pages are expensive? |O
They are. (https://www.cadsoftusa.com/shop/pricing/?language=en)
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Mother of God that is one horrid analog schematic. What is with these people who think schematic pages are expensive? |O
They are. (https://www.cadsoftusa.com/shop/pricing/?language=en)
:wtf: 575 for sch +pcb with 99 sheets of glorified pencil and paper . Here i was thinking eagle was cheap ... as in like 199$ ...
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Mother of God that is one horrid analog schematic. What is with these people who think schematic pages are expensive? |O
They are. (https://www.cadsoftusa.com/shop/pricing/?language=en)
:wtf: 575 for sch +pcb with 99 sheets of glorified pencil and paper . Here i was thinking eagle was cheap ... as in like 199$ ...
Even the hobby package is pretty expensive. I could get them hundreds (potentially many thousands..) of sales of that package at $50. At $169 with no way to recoup it? Not likely.
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I attached an example of an , in my opinion, -clean- schematic. ( i drew it according to my rules , which are based on what i see in other professional schematics ( like the older HP schematics, some Philips service manuals for their hi-end tv and audio gear, and others))
It's only one page from a larger design but it gives you an idea of what should be done.
- The incoming supplies , their filtering and decoupling are in one spot.
- A customized symbol with spread and reordered pins to avoid wire spaghetti. (David was right. This was made in DXP .. so they have had reordering since over 10 years ago... )
- Attention to the positioning of parts , designators and other decals.
- Correct, and only allowed, usage of diagonal wires to avoid 'spaghetti' (in the combiner hybrid) and to indicate Kelvin connections. (on the IC pins)
- no ambiguous cross junctions, only T-junctions.
Schematics like this are easy to follow. There is no guessing what is wired to what else, and any special things are immediately visible ( like the double diagonal twist in the hybrid splitter.)
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Wow, this is amazing
Wait until you see AD 14 in a few weeks. That will be jaw dropping and eye popping .... We ( the silicon valley users group) got an overview last week at the Marriott hotel here. (with an excellent lunch buffet to boot).
It gets some capabilities that pushes Altium into a whole new category of PCB tools... yes, these are back to the core of schematic and PCB updates. They are getting serious ...
To paraphrase Dr. Brown : When this thing hits 88 miles an hour you are going to see some serious sh...
The first step has been taken in AD14 with a hint to the future : they have an Eagle importer (sch and brd) in AD14 ... and other importers are in the works... hint hint...
Early next year (target February) another big game changer is coming with the new pricing model... with a few 'entry levels' ... hint hint
And that's all i'm going to say about that. Go read that shareholder overview that was posted in a topic here a few weeks ago and connect the dots...
Thats some good news. I signed up for the preview presentation on the 20th... the email said it was about vault management/cloud BS but this could be cool.
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I would like to see more "best drawn" examples or best-practice examples if people have them. Cheers :-+
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i just posted one 5 messages ago. has a pdf attachment. go look at it.
here it is once more :
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I have a book call "Experiments with EPROMs" by Dave Prochnow. The schematics in there are just rectangles representing pin-outs of ICs and their connections to each other without any logic symbol! Horrid - dunno why I kept it!
Also I once had to fault find a Tiawanese made PSU using a schematic that used no recognisable convention and I actually blew up the damn board out of misunderstanding the diagram!
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i just posted one 5 messages ago. has a pdf attachment. go look at it.
here it is once more :
Thanks, it was your post that prompted me to ask for more examples!
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I would like to see more "best drawn" examples or best-practice examples if people have them. Cheers :-+
Have a look at the ones for older HP test gear.
Also, the schematics in this Hitachi scope service manual are good. What I really like is that component numbering has been done on a clustering basis, so that R84x will be in the same block at TR84x and C84x. Saves a lot of hunting when fault finding.
http://skory.z-net.hu/alkatresz/hitachi_V-211-212-222-422_service_manual.pdf (http://skory.z-net.hu/alkatresz/hitachi_V-211-212-222-422_service_manual.pdf)
I've worked on one job recently where the schematic was 25 pages long which used a similar principal. All ref des were four digits, with the first two being the sheet number.
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Here is a schematic I drew for an isolated DC-DC converter. Not finished yet.
(prototype electric drivetrain.)
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Most Crowded:
(http://blog.iteadstudio.com/wp-content/uploads/image/2011_03/ds203-mini-dso-dso-quad-start-production-now_3.jpg)
Scarily, I knew exactly what that diagram was. A few months ago I dissected and simulated the analogue input to see just how bad it's performance was. Despite being crowded it is at least quite readable. Unlike the increasing number of corporate engineers who insist on putting one IC per page. Aaargh!
But that schematic is ALSO a schoolbook example of how NOT to draw schematics. they just had to cram everything on a 11x17 ...
split that sucker in an analog section and a digital section. a nice bus interconnects the two.
and for 'f#$% sake : make CUSTOM symbols to get rid of the wire spaghetti. make little block diagrams inside the ic symbols to show what is inside.
Anyone who can't follow that schematic should probably take up fishing instead.
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Here is a schematic I drew for an isolated DC-DC converter. Not finished yet.
(prototype electric drivetrain.)
At a glance it looks good to me. :)
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Here is a schematic I drew for an isolated DC-DC converter. Not finished yet.
(prototype electric drivetrain.)
pretty clean but there is some small improvement possible.
r3/d5/q2/r4/r5/c21 for example.
if you move the FB pin from the left to the righ and install it above the gate drive) of the mosfet ( pin 16) and make the regulator chip taller
you can tap the r3 node at pin 2 of q1
the base of q2 is tapped just right of z1
this removes 4 crossing wires completely.
rotate r22 horizontaland to the right . removes a crossing
rtate c22 to the right. rotate r9 and c24 horizontal and to the right . you can now connect right side of c22 r9 c24 together and plonk to ground with 1 power object.
lifting the wire from inbetween the fuse and d1 : see how it now goes down and crosse two hirozntal traces, then goes left and makes another corss. by taking the horizontal section and pullin it above r2 you eliminate 3 line crossing.
i'd say overall this is a clean drawing. i wuold clean out the stuff i mentioned above and i would line up the optocouplers so the split in the optos coincides vertically with the core of the transformer.
A vertical dotted line then shows the isolation barrier.
i like the callouts with some voltages.
question : i see where LB+ of your regulator is connected (between C8 and C9 . i can't find the +5VP though ...
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Anyone who can't follow that schematic should probably take up fishing instead.
it's not a matter of following. it is too cramped , there is wire spaghetti. it overwhelms at first sight .
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I would like to see more "best drawn" examples or best-practice examples if people have them. Cheers :-+
Just a few.
http://www.users.on.net/~glenk/ddac/ClockGeneratorBoard2.pdf (http://www.users.on.net/~glenk/ddac/ClockGeneratorBoard2.pdf)
https://www.eevblog.com/forum/projects/home-brew-analog-computer-system/?action=dlattach;attach=35348 (https://www.eevblog.com/forum/projects/home-brew-analog-computer-system/?action=dlattach;attach=35348)
http://www.users.on.net/~glenk/200vbuck/200vbuck.pdf (http://www.users.on.net/~glenk/200vbuck/200vbuck.pdf)
http://www.users.on.net/~glenk/thd/autotune.pdf (http://www.users.on.net/~glenk/thd/autotune.pdf)
http://www.users.on.net/~glenk/asamk1/vga2.gif (http://www.users.on.net/~glenk/asamk1/vga2.gif)
Dunno about pretensions of "best drawn", but I think they are pretty legible. I like to print the larger, more complex schematic to large sheets. I loathe excessively broken down schematics printed to multiple A4 pages.
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most of those are legible and clean , but the large one suffer form the 'let's cram it all on one page' disease. (amplifier and that THD system)
break it in manageable chunks.
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If the components can all fit into a single PCB, then they can all fit into a single sheet :P
A complex, single board schematic prints out nicely to an A3 or an A2, both of which fold up nice an neat A4-size for filing. If I have to fault find something that I haven't looked at for a long time, a large, complete schematic folded out on the bench is much better than an A4 booklet which one has to continuously flick through tracing out nets.
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If the components can all fit into a single PCB, then they can all fit into a single sheet :P
I've worked on a board with 5000 components on it. I'm glad that the schematic was printed on more than one sheet.
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Well, my half serious comment was in reference to the schematics I posted.
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On the topic of badly drawn schematics, some of the worst are from the vintage era of radio. There seemed to be a phase where the draftsman would use his stencil to draw in the major components, evenly spread out across the page, and then proceed to wire everything up. One rainy weekend a while ago I got fed up tracing the vintage wiring schematic spaghetti for some old units I was working on restoring, and re-drew them a bit neater:
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On the topic of badly drawn schematics, some of the worst are from the vintage era of radio. There seemed to be a phase where the draftsman would use his stencil to draw in the major components, evenly spread out across the page, and then proceed to wire everything up.
At a time when there wasn't CAD, not surprising; the alternative of erasing many times or getting a new sheet and starting over is not really practical. Some of the early TV schematics weren't too bad, however.
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At a time when there wasn't CAD, not surprising; the alternative of erasing many times or getting a new sheet and starting over is not really practical.
Really, though, how hard would it be to sketch it out roughly first to figure out where things should go?
I like your style, Glen. This is remarkably easy to follow, and having seen a good few of these old RF schematics myself, I can imagine how shitty it was initially :scared:
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It wouldn't surprise me if drafting was a different person's duty than designing. Have you ever drawn out a schematic of a circuit you didn't design?
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Of course it was, but the designer would have had to sketch out the circuit first so the drafter knew what he was supposed to draw...
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On the topic of badly drawn schematics, some of the worst are from the vintage era of radio. There seemed to be a phase where the draftsman would use his stencil to draw in the major components, evenly spread out across the page, and then proceed to wire everything up.
At a time when there wasn't CAD, not surprising; the alternative of erasing many times or getting a new sheet and starting over is not really practical. Some of the early TV schematics weren't too bad, however.
Well sure, but economic rationalizations in wartime production had a great deal more to do with it than the lack of CAD. Have a look at the some of the early Tektronix manuals for examples of properly drawn schematics by the traditional draftsman who had the time and equipment to do it right.
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Of course it was, but the designer would have had to sketch out the circuit first so the drafter knew what he was supposed to draw...
One place I worked at the drafter would do the schematic from the designers sketches. It was the designers job to keep it updated and it would usually be necessary to add a few blocks, turning a nicely spaced, well drawn schematic into a mess.
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Lots of little things can add to make a schematic worse, for example:
Manufactures who shun standard components and call them by their own part number, like HP. If a part is selected then say so, and why it is selected.
People who draw interconnecting lines that join at a cross, is that a dot or not? Just how many hours have been wasted by that silly method of drawing?
Inputs on the left, outputs on the right, usually. But would you split a microcontroller port so some on the left, some on the right of the symbol if the port has inputs and outputs?
Am I alone in finding the new, 1980s, logic symbols to be meaningless? That a symbol has external connections to the symbol outline seems just foolish.
Meaningful signal names.
Programmable devices described by what they do.
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Am I alone in finding the new, 1980s, logic symbols to be meaningless? That a symbol has external connections to the symbol outline seems just foolish.
Not sure what you mean here. Can you give an example?
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That's just lazy and dumb
What is? Sorry, it wasn't clear.
Assigning pins based solely on what looks neat in the schematic
Software is easy to fix.
Well, it depends. There are often restrictions on things like what kind of interrupts are available on a given pin, how many timers are available per port for PWM output and so forth.
That's about fully understanding the device, and what things can and cant be swapped ( and if necessary hacking up a quick prototype to test anything that's not clear in the datasheet)
When your code is filling up a 256k flash ROM and has to do some very complex stuff things like that can make it excessively complex and fragile. We are not talking Arduino sketches flashing some LEDs here.
If pin assignments make a significant difference to a 256k code base, you're probably doing it wrong
The hardware guys never read the detail in the datasheets either.
For example on AVRs with SPI ports the Slave Select pin forces the SPI peripheral into slave mode when pulled low, so you can't use it as a general purpose input.
I've been caught by that one, but fortunately it was just a DIP switch so I could work around it by setting it as an output when SPI stuff was happening.
All of this is about knowing and understanding the part, and where having the same person doing hardware and (at least the low-level) software makes more sense than seperating the two.
At the very least, hardware people should be able to write enough code to demonstrate that the hardware does what it should before throwing it over the wall to the code monkeys.
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Well, my half serious comment was in reference to the schematics I posted.
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On the topic of badly drawn schematics, some of the worst are from the vintage era of radio. There seemed to be a phase where the draftsman would use his stencil to draw in the major components, evenly spread out across the page, and then proceed to wire everything up. One rainy weekend a while ago I got fed up tracing the vintage wiring schematic spaghetti for some old units I was working on restoring, and re-drew them a bit neater:
Those are some nice sheet mans, IMO one very under appreciated metric of any engineering diagram is whether they remain informative when converted to black and white. This can be critical if they need to be photocopied. I've read too many IEEE papers where the graphs are useless because the author submitted them converted to B&W.
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Good news is, the power supply is now fixed.
I accidentally disconnected one of the wires in the cable bundle going from the main board to power supply. Looks like it's related to backlight on/off as the backlight now stays on except during standby. Ah well. Tracing out exactly where that wire went is a nightmare because the colours are not coordinated. Different colours for the same voltages. Red and orange frequently used for ground. Ugh.
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Many of the pictures posted of horrible schematics look very much like what I deal with every single day in consumer electronics. Large multi-channel receivers, processors, etc. The service data is at least usable for the most part, but much time is often wasted merely getting one's bearings and learning a given manufacturers quirks of notation, naming protocols etc.
Sometimes they are simply evil, in schematic and in physical execution, which by the way is what some of the designers deserve. The most failure prone parts are often hidden under a maze of CAD-designed inter-connected boards when they need not be. For example, crap 7812 and 7912 failure-prone VERY CHEAP Korean voltage regulators which could have been located where it does not take three hours in and out to replace. Merely finding test points for them was a lengthy and frustrating process. Eventually had to give up on a couple of the test points and just tear into the thing and replace them all.
Recent Sony electronic service data is excellent, many with clickable links to zoom you from one connector to it's mate on another board, from the IC position on the board to the parts list and part number, back to the schematic, and so on.
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I would say most disconnected looks like my scratch paper in the lab.
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The new, 1980, logic symbols.
Look at a suitable TI TTL data book, try the 7446/7/8 or 74184 etc etc. The symbol doesn't stop at the outer boundary line, but has wires and joins.
Look at the 74161, a basic counter, where do the pin names go? In the good old days you just labeled pin 15 as RCO, now it seems to be called 3CT=15.
Whilst the new symbols are all logically constructed, they are not obvious and will get worse as circuits are copied.
Have to say that never really seen them used much though, but that is probably reserved for companies that are required to use them on all documentation.