I really hate these 'lego' schematics with no connections - the biggest annoyance is it's hard to tell how many nodes are connected to any given point.
Given that this laziness is now so widespread, something that would improve them is if next to the node name, it also showed how many other nodes were connected to that one. This could be done automatically by the tool. Another possible enhancement would be if the nodes had short lines pointing in the direction of each node it's connected to, to make it easier to find.
What's the standard for bypass caps? I usually put them right next to the supply pins of each individual IC, so you can easily see which cap belongs to which IC. I have often seen them put separately, like you just mentioned. Are there any written/unwritten rules that I'm not aware of?
That's something I don't care about as it doesn't affect the understanding fo the functionality.
I am repairing an LCD TV and this is the schematic I have to use.
It's already a miracle you actually have a schematic. At work I even have trouble finding them for boards that were designed in-house...
Considering everything is throw-away these days I would only expect a list of part numbers for the individual boards
I am repairing an LCD TV and this is the schematic I have to use.
It's already a miracle you actually have a schematic. At work I even have trouble finding them for boards that were designed in-house...
Considering everything is throw-away these days I would only expect a list of part numbers for the individual boards
That certainly doesn't look like a schematic for servicing, or for anything other than internal use during design. Never overestimate the security of Chinese corporate networks... or underestimate the tenacity of those who want to get schematics.
Vestel is a Turkish company that produce junk TVs, among other electronics. I acquired the schematic along with hundreds of others.
Looks like one of the five paralleled UF5402s has shorted, taking the MOSFET, PFC IC and ten other components with it. And to think -- Toshiba, Sharp and Hitachi -- formerly respectable brands -- are now re-badging this same Vestel chassis!
Ugh. At least the TV was free.
Some schematics are auto drawn, there is a tool called Cadence system architect the allows you to connect nets in a spreadsheet and then it auto gens a schematic routed with net names only. It makes sense for digital net lists like TVs, PC motherboard and dimms but not so much for mixed signal designs.
I have to say that honestly I prefer to use net names because I hate trying to follow a line snaking around a page with 20 other nets adjacent and intersecting.
That "most crowded" schematic was ok organized in my opinion... Not a fan of flipping through endless pages of schematics just for gratuitous white space.
Analog and rf circuits flow much better so yes direct connections are preferred here.
I guess the one thing that is needed if you use net names is a proper crefer need to annotate names onto each dangle.
It is a matter of style and preference. At the end of the day, a logical flow is important and all good circuits have a logical flow...
The OP schematic looks indeed like it was put together from small verified working snippets. I dont think it is that horrible. The worst I've seen was a bunch of jelly bean transistors, resistors 74 series IC dropped on one page all connected together without proper description and logical order. Even the connectors' functions were not obvious.
The problem with the "most crowded" is basically the improper use of busses. I made more crowded A3 pages, but there was a logical way of the signaling, everything went from left to right, without crossing, each block labeled, and having proper symbols.
I don't have a problem with the busses in the "most crowded". It's as graceful a way as any other to draw a large number of digital signals. My problem with net names is that I can't see everything that connects to a signal without reading every single net name on the whole diagram. At least with the bus, the digital signals are confined to a section.
Grouping digital signals IMHO is OK. I often use buses for things like SPI. It's not the "traditional" application, but really, very few circuits have parallel A/D buses anymore - might as well find a new application for the tool.
My other pet hate is when the EE decides to use certain pins on the microcontroller because it makes drawing the schematic easier, even though it makes my life as software engineer harder. That's one reason why I like to be involved with the hardware design as much as possible, or just do it myself.
That's just lazy and dumb
Ideally the schematic software should allow you to quickly and easily easily move pins around on a symbol to make it neater - I'm not aware of any tools that allow you to do this, though I've not used many different ones.
A much better approach is to choose pins that make the PCB layout nicer (shorter traces, fewer vias, better EMC, maybe even fewer layers). Unfortunately tool support for determining pinouts at layout time (other than by back-annotating pin-swaps) isn't generally good IME.
This is why I usually do the PCB first & (maybe) the schematic afterwards, when all the details have been nailed down. Although some software allows for pin-swaps on things like equivalent gates (if the library has been set up right), It's just too hard to effectively express the constraints on MCU pin swappability, especially as these will depend on design details like which peripherals are used.
Software is easy to fix.
I like Mike's idea of putting net connection counts right after the net name on the schematic. It'd make gauging fanouts easier. I'll admit, yeah, I do the "huge mess of random nets" thing with large FPGAs, swapping i/o to make the routing job easier.
My other pet hate is when the EE decides to use certain pins on the microcontroller because it makes drawing the schematic easier, even though it makes my life as software engineer harder. That's one reason why I like to be involved with the hardware design as much as possible, or just do it myself.
I usually first connect it so it looks good on the schematic, then rearrange it so it's convenient to route the PCB and I later make modifications to optimize bit juggling in software.
Software does get the last word, as long as that doesn't cause a bigger inconvenience with the layout.
So what exactly are the problems with the "Most Lame" example? Other than the fact that there is only one sheet (which if I had to guess was due to using the Lite version of Eagle which only allows one sheet per schematic).
The circuit seems to be divided up into functional areas. Sure some are really small (like the reset), but it seems consistent?
Just a young player looking out for traps.
Most Crowded:
Scarily, I knew exactly what that diagram was. A few months ago I dissected and simulated the analogue input to see just how bad it's performance was. Despite being crowded it is at least quite readable. Unlike the increasing number of corporate engineers who insist on putting one IC per page. Aaargh!
This schematic looks fine to me. It looks very easy to read and compact. But why are there a kaggillion pins from the to ic's on the same buss?
My other pet hate is when the EE decides to use certain pins on the microcontroller because it makes drawing the schematic easier, even though it makes my life as software engineer harder. That's one reason why I like to be involved with the hardware design as much as possible, or just do it myself.
I had a boss, who makes software also, and lot of times he ordered us to modify hardware, just to make his life easier. Every now and than we had to put extra hardware on the board, just to make the software super fancy. We actually payed for this. Once I had to rename 2-3 times my signals on a 15+ page schematic, just because he changed them in the software, and I had hard time explaining him, that I cannot name the signal the same before and after a series termination resistor. I remember, once he tried to force me, to put an extra XOR gate on two signals coming out of an FPGA
which was never used anywhere else. Total incompetence.
I don't wish to anyone to have the same experience.
So what exactly are the problems with the "Most Lame" example?
Because of the acute netnameitis, you cannot tell by looking at one part of the schematic what else it connects to. If I'm trying to troubleshoot that circuit, I don't want to just see that there's a MOSFET gate switched by a signal E0-HEAT, I want to know
what sources that signal and what
else the signal goes to. The nice thing about a line is that you can trace it and see every single thing it touches.
This is the worst schematic that I have ever seen. This one is made by the queen arduino herself. It even has overlapping parts and diagonal nets!
http://www.ladyada.net/media/wavebubble/cigpack-main%20rc1.pdf
You just provided an example for the crap I was referring to in one of my previous posts:
I've seen many schematics where there were wires drawn across symbols. Like wires connecting to pins from the inside of the symbol. Coincidentally, they were all drawn in Eagle. 
Another thing that really ticks me off is text placed over connections, so you have trouble both reading that text and following a signal path. Again, same schematic.
I work in a company that has been around for a long time. When they first started doing PCBs it was decided that the Drawing Office would lay them out as they had full drawing boards and were used to doing drawings without messing them up.
Fast forward 30 years and the mandate that "Drawing Office does the PCB artwork" morphs into "Mechanical Designers do the PCB layout". As a result, they also maintain the electronic symbols so what we get as a schematic symbol turns into a generic box with the legs around it - regardless of were the input / outputs are. Try complaining that it makes the schematic unreadable and they explain that as they don't understand the schematic they don't expect anyone else to.
I've produced some poor schematics in my time. I'm quite a disorganised and messy person and when I first started schematics were drawn by hand. I could do a reasonable job to start with, but with a project that ran for four years extra blocks had to be added usually where there wasn't really room for them.
What's the standard for bypass caps? I usually put them right next to the supply pins of each individual IC, so you can easily see which cap belongs to which IC. I have often seen them put separately, like you just mentioned. Are there any written/unwritten rules that I'm not aware of?
Unwritten rule is they go next to the chip or device to be bypassed, so the board layout person (even if they same person) knows where they go.
Not to do so rightfully leads to pubic humiliation from your peers.
I believe that there's a European law against pubic humiliation.
Ideally the schematic software should allow you to quickly and easily easily move pins around on a symbol to make it neater - I'm not aware of any tools that allow you to do this, though I've not used many different ones.
I move pins around on schematic symbols in Altium all the time, but mainly for micros. No need to go make a custom version of that symbol for that schematic. Just unlock the pins (for that part) and drag them wherever you want. So easy and can make a massive difference to the flow of a schematic.
Many many years ago I used to do the board layout then do the schematic. Way too easy to screw up imo. Now, even for simple projects I do the schematic first. Sometimes it starts out with just a few critical parts (connectors, transformer and other large parts). This is so I can get a feel for they board size and how the I/O will work out. Then I'll add more to the schematic, import the changes and continue the board design. Quite often the schematic changes according to the board space limitations.
Yeah nets across a symbol makes me very in comfortable
Other that those few nets, not bad style in my opinion. I wonder if they went wonky when generating the PDF or a last minute drag of a symbol. Surely no one would do that consciously.
I think everyone's got it right, proper layout is first priority, software ease is second, schematic hygiene third. Although software needs to justify their request with an explanation that I like otherwise tough luck...
...with one page just for bypass caps etc.
Hey, now.
Where applicable, the bypass cap is on the IC. But some designs have more "dispersed" on the board. I add them so the layout gets them. I go back and delete what I don't feel is necessary. (I'm always the layout guy)
This one's fun to troubleshoot from...
Mother of God that is one horrid analog schematic. What is with these people who think schematic pages are expensive?
Most Crowded:
Scarily, I knew exactly what that diagram was. A few months ago I dissected and simulated the analogue input to see just how bad it's performance was. Despite being crowded it is at least quite readable. Unlike the increasing number of corporate engineers who insist on putting one IC per page. Aaargh!
But that schematic is ALSO a schoolbook example of how NOT to draw schematics. they just had to cram everything on a 11x17 ...
split that sucker in an analog section and a digital section. a nice bus interconnects the two.
and for 'f#$% sake : make CUSTOM symbols to get rid of the wire spaghetti. make little block diagrams inside the ic symbols to show what is inside.
Ideally the schematic software should allow you to quickly and easily easily move pins around on a symbol to make it neater - I'm not aware of any tools that allow you to do this
Altium. Since version 11.something. Simply double click a symbol, untick the 'lock pins' checkbox and you can move em around. you can even rename or renumber pins , i use this all the time