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| langwadt:
--- Quote from: EEVblog on October 18, 2021, 11:07:19 am --- --- Quote from: sandalcandal on October 18, 2021, 06:38:50 am ---User manual here: https://www.totalphase.com/support/articles/360023273894-Advanced-Cable-Tester-v2-User-Manual Shows screenshot the eye diagram based signal integrity check. --- End quote --- Seems to claim signal integrity. --- Quote ---http://A complete battery of tests is performed when a cable is plugged in. These tests include: Continuity/Wiring - cable specific and customizable DC Resistance - pin and wire measurements, Rd, Rp, Ra, and more Signal Integrity - configurable from 518 MHz to 12.8 GHz on up to 5 differential pairs E-Marker Verification - PD2/PD3 verification Apple MFi Mandated Tests - Over Voltage Protection, Quiescent Current, Source Measurement Unit Tests --- End quote --- --- Quote ---http://Table 10 : Signal Integrity Test Report Data Rate Speed of the data signal used in the test in Mbits per second Transmit Pair Transmitter plug and pins Receive Pair Receiver plug and pins HEO Horizontal Eye Opening is a percentage value that indicates what percentage of the reference frame of the eye is open across the widest section. The Expected is the minimum open percentage that will pass the test and is generated based on the insertion loss curve specified in the test profile. The Measured is the actual percentage open. VEO Vertical Eye Opening is a percentage value that indicates what percentage of the reference frame of the eye is open across the widest section. The Expected is the minimum open percentage that will pass the test and is generated based on the insertion loss curve specified in the test profile. The Measured is the actual percentage open. Eye Image If lock was achieved on the indicated differential pair, the eye image will be displayed. The eye image will include the mask to provide a reference for the HEO and VEO values. If lock was not achieved, a no-lock image will be displayed. --- End quote --- Kinda sounds like it might not be a real high speed ADC measurement, but more of an implied result based on comparator threshold measurements maybe? At the claimed 12.8GHz you'd need some insanely fast ADC stuff to get a real time eye diagram. I'm not seeing that capability on that board. And then you have that internal board to board connection for the various modules. --- End quote --- with a repetitive signal you can use "equivalent time sampling" so only the analog frontend and sample-hold needs to be that fast |
| EEVblog:
--- Quote from: langwadt on October 18, 2021, 11:42:20 am ---with a repetitive signal you can use "equivalent time sampling" so only the analog frontend and sample-hold needs to be that fast --- End quote --- Yes, but at these speeds and the need quantify a 12.5GHz signals eye diagram, ETS and the associated trigger jitter becomes problematic. Possible of course, but again, I'm not seeing the hardware there, unless it's hidden away somewhere else. EDIT: I presume there must be something under the metal can on the front module. |
| ejeffrey:
It's true that jitter is an issue for ETS but if this is dedicated for measuring high speed links you would be able to use the clock/data recovery circuit within your receiver to provide a low jitter trigger. Some FPGAs have a built in eye scan capability as described here: https://wiki.analog.com/resources/tools-software/linux-software/jesd_eye_scan Basically you run your standard CDR signal for BER testing and a second sampler with an adjustable relative delay and threshold. Then you compare the data between them. If it matches that is a point in the eye. This let's you build up a map of the eye This was developed not so much to save test equipment but because for really high speed links you want to measure the eye at the FPGA input pin not on an external connector. These days am FPGA doesn't need to be particularly beefy to support high speed transceivers although >= 20 Gb/s needed for thunderbolt are still relatively high end. You could also use the CDR clock and a programmable delay to trigger an external ADC. This would be a lot faster than scanning a threshold. An ADC for ETS doesn't need to be particularly large or power hungry, and the AFE needed is rather minimal since the signal is already the correct amplitude and differential. It's obvious the video is not intended to include a technical teardown like Dave would do and I would love to see. It's hard to tell exactly what is going on but there are definitely options besides a realtime oscilloscope that costs as much as a house. |
| vaualbus:
So at the end we are sure they "cheat" in the sense that they not do BER measure but look at some other signal parameters. But yes I agree a full teardown would be very cool! |
| wraper:
--- Quote from: vaualbus on October 18, 2021, 04:03:45 pm ---So at the end we are sure they "cheat" in the sense that they not do BER measure --- End quote --- BER does not tell how good the cable is and how close it is to failing, only that it's crappy enough to cause data loss. |
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