Is this product a BS didn't it?

[vaualbus]

I watched last week this video
and I was already convinced that the device was a scam. How you test an USB3 cable and produce "eye diagram" without at least a fast FPGA and fast ADC/DAC on which I would assume you need a pretty big heatsink?
I recall I went to a keysight meeting a while ago where they show their at the time top of the line scopes (63Ghz @80 Gbs/s or what was) doing automatically validation and compliance test on USB3 buses, that is what you need 
So I guess that machine is trying to do a frequency analyzes of the cable and match the results against a know database? And produce "fake" eye diagram?
Your opinion is appreciate because I got already angry on the "wrong" eye diagram definition that was given on the vide.

[wraper]

You don't need some super fast ADC for something like that. Working as sampling scope is more that enough for such application.

[vaualbus]

Still you do sampling ok, but can you characterize 10gbs lines? You have to at least generate such PRBS sequence?

[langwadt]

Still you do sampling ok, but can you characterize 10gbs lines? You have to at least generate such PRBS sequence?

you can probably do that with just the phy for the various standards

[eti]

As clever as Linus is, he is NOT an electronics or test eqt channel, and were I him, I'd surely delegate that kind of approval to someone live Dave, or countless members here.

[langwadt]

As clever as Linus is, he is NOT an electronics or test eqt channel, and were I him, I'd surely delegate that kind of approval to someone live Dave, or countless members here.

the little I've seen of him, he seems to "review" lots of solutions looking for a problem, and either very expensive or niche for such a large audience. But as long as the check clears ....

[Bassman59]

TotalPhase products are solid.

And this cable tester is $15,000 so it is reasonable to assume that it has the necessary hardware to do the tests.

[wraper]

As clever as Linus is, he is NOT an electronics or test eqt channel, and were I him, I'd surely delegate that kind of approval to someone live Dave, or countless members here.

And what equipment Dave has to make such measurements? Not to say some specialized tool which will do it very fast and hassle free. What incentive he has to spend time on this to begin with?

[EEVblog]

I have not watched the video, but right off the bat I'd add that you can very usefully test cables by simply flogging the phy at full speed and lookind for bad packets etc.
I've done this with 10Gb ethernet interface FPGA designs. Just flogged it for a hours and get an accumulated error count. No need for actual quantified signal integrity measurement.

[EEVblog]

Watched a bit of it.
Doesn't look like signal integrity measurement to me. So likely just packet error testing.

[ejeffrey]

I recall I went to a keysight meeting a while ago where they show their at the time top of the line scopes (63Ghz @80 Gbs/s or what was) doing automatically validation and compliance test on USB3 buses, that is what you need.

Verifying that a USB controller is properly implementing the protocol is orders of magnitude more complex than testing a cable. I don't know anything about this device but nothing there seems particularly implausible. 

[sandalcandal]

I have not watched the video, but right off the bat I'd add that you can very usefully test cables by simply flogging the phy at full speed and lookind for bad packets etc.
I've done this with 10Gb ethernet interface FPGA designs. Just flogged it for a hours and get an accumulated error count. No need for actual quantified signal integrity measurement.

A few hours per cable seems excessive. The device shown does a decent looking set of tests in under a minute (?) and also produces some eye diagrams. However LTT didn't actually look closely at the technical details of the testing, that would probably be lost on their audience. They did give a decent layman's intro of what an eye diagram is however.

[sandalcandal]

User manual here: https://www.totalphase.com/support/articles/360023273894-Advanced-Cable-Tester-v2-User-Manual
Shows screenshot the eye diagram based signal integrity check.

User manual also goes over the other tests the device does.
I remember them showing the eye diagrams in the LTT video too.

Seems a bit knee jerk to call it BS. Looks like an alright bit of industrial test gear for on the lower end of specialised test gear price. It does feel a bit out of place on the consumer oriented LTT channel though Linus mentioned good motivation for having one. They also did hire some "real" engineers recently that have popped up in a few videos giving advice.

[eti]

As clever as Linus is, he is NOT an electronics or test eqt channel, and were I him, I'd surely delegate that kind of approval to someone live Dave, or countless members here.

And what equipment Dave has to make such measurements? Not to say some specialized tool which will do it very fast and hassle free. What incentive he has to spend time on this to begin with?

Dave is an EXTREMELY experienced, qualified electronic engineer with many decades of experiences, whereas Mr Sebastian is a youngster, and with all respect, a bloke that plugs modules together and tests them - and yes that is a job requiring experience, but unless I am lacking info regarding Mr Sebastian, he IS NOT an electronics engineer (I've seen plenty of times where he appears rather clumsy in his videos - either he IS, or intends to portray that image... although... WHY he'd want to do so is baffling)

Your open-ended Q regarding Dave's "incentive" et cetera... sorry, but what? I am confused as to what you want to know - a rather poorly worded question?

[wraper]

Dave is an EXTREMELY experienced, qualified electronic engineer with many decades of experiences, whereas Mr Sebastian is a youngster, and with all respect, a bloke that plugs modules together and tests them - and yes that is a job requiring experience, but unless I am lacking info regarding Mr Sebastian, he IS NOT an electronics engineer (I've seen plenty of times where he appears rather clumsy in his videos - either he IS, or intends to portray that image... although... WHY he'd want to do so is baffling)

Good enough explanation for a layman (target audience). And so what? This tester does not require any experience to get a result of passing or not. Plug the cable and run the test.

Your open-ended Q regarding Dave's "incentive" et cetera... sorry, but what? I am confused as to what you want to know - a rather poorly worded question?

What does Dave get from testing tons of cables? EEVBLOG is not even a computer hardware channel. So making cable comparison for non target audience makes little sense. Of course he could make a video about the eye diagram (and I think he actually did before) and testing a few cables, but that's it.

[newbrain]

A few hours per cable seems excessive.

It depend on the needs.
If you need to have a BER (bit error rate) estimation with a good confidence level, the time grows very fast if you have no errors on a fast interface.

If you want to be 95% sure that BER is less than 1 in 10^12 (the standard value for 10G Ethernet), you need to transmit:
    10^12 × -ln(1-0.95) ~= 3 × 10^12 bit

On a 10 Gb/s interface that is just 5 minutes, but as soon as one needs better BER or CL, the time goes up, e.g. for 10^-14 BER, 99% CL we are up to more than 12 hours!

[sandalcandal]

A few hours per cable seems excessive.

It depend on the needs.
If you need to have a BER (bit error rate) estimation with a good confidence level, the time grows very fast if you have no errors on a fast interface.

If you want to be 95% sure that BER is less than 1 in 10^12 (the standard value for 10G Ethernet), you need to transmit:
    10^12 × -ln(1-0.95) ~= 3 × 10^12 bit

On a 10 Gb/s interface that is just 5 minutes, but as soon as one needs better BER or CL, the time goes up, e.g. for 10^-14 BER, 99% CL we are up to more than 12 hours!

Well I can't deny that's the "proper" way to directly validate BER [for a complete transmitter-receiver system]. I was thinking about for quick partial validation a look at the eye diagram seems more common though I haven't done signal processing stuff since undergrad.

Tektronix app note on using eye diagrams for BER https://download.tek.com/document/65W_26019_0_Letter.pdf


Edit: Dug out the slide from the photonics course I took at ANU. A formula was given for calculating BER from eye diagram reading assuming Gaussian noise.
Edit2: Also assuming decision point and decision levels for the receiver.

[tszaboo]

As clever as Linus is, he is NOT an electronics or test eqt channel, and were I him, I'd surely delegate that kind of approval to someone live Dave, or countless members here.

And what equipment Dave has to make such measurements? Not to say some specialized tool which will do it very fast and hassle free. What incentive he has to spend time on this to begin with?

Dave is an EXTREMELY experienced, qualified electronic engineer with many decades of experiences, whereas Mr Sebastian is a youngster, and with all respect, a bloke that plugs modules together and tests them - and yes that is a job requiring experience, but unless I am lacking info regarding Mr Sebastian, he IS NOT an electronics engineer (I've seen plenty of times where he appears rather clumsy in his videos - either he IS, or intends to portray that image... although... WHY he'd want to do so is baffling)

Your open-ended Q regarding Dave's "incentive" et cetera... sorry, but what? I am confused as to what you want to know - a rather poorly worded question?

You don't need to be an EE to test a cable.
The equipment generates a test report, and he was focusing on the Pass/Fail aspect of it. That is a lab technician job, the qualifications for those are high school diploma.

Watched a bit of it.
Doesn't look like signal integrity measurement to me. So likely just packet error testing.

Thanks for posting this picture.
I think it is using the MAX3987
8.5Gbps Quad Equalizer and Preemphasis Drive

The package, high speed signals pinout seems to match.

[EEVblog]

User manual here: https://www.totalphase.com/support/articles/360023273894-Advanced-Cable-Tester-v2-User-Manual
Shows screenshot the eye diagram based signal integrity check.

Seems to claim signal integrity.

http://A complete battery of tests is performed when a cable is plugged in. These tests include:

Continuity/Wiring - cable specific and customizable
DC Resistance - pin and wire measurements, Rd, Rp, Ra, and more
Signal Integrity - configurable from 518 MHz to 12.8 GHz on up to 5 differential pairs
E-Marker Verification - PD2/PD3 verification
Apple MFi Mandated Tests - Over Voltage Protection, Quiescent Current, Source Measurement Unit Tests

http://Table 10 : Signal Integrity Test Report
Data Rate   Speed of the data signal used in the test in Mbits per second
Transmit Pair   Transmitter plug and pins
Receive Pair   Receiver plug and pins
HEO   Horizontal Eye Opening is a percentage value that indicates what percentage of the reference frame of the eye is open across the widest section. The Expected is the minimum open percentage that will pass the test and is generated based on the insertion loss curve specified in the test profile. The Measured is the actual percentage open.
VEO   Vertical Eye Opening is a percentage value that indicates what percentage of the reference frame of the eye is open across the widest section. The Expected is the minimum open percentage that will pass the test and is generated based on the insertion loss curve specified in the test profile. The Measured is the actual percentage open.
Eye Image   If lock was achieved on the indicated differential pair, the eye image will be displayed. The eye image will include the mask to provide a reference for the HEO and VEO values.

If lock was not achieved, a no-lock image will be displayed.

Kinda sounds like it might not be a real high speed ADC measurement, but more of an implied result based on comparator threshold measurements maybe?
At the claimed 12.8GHz you'd need some insanely fast ADC stuff to get a real time eye diagram. I'm not seeing that capability on that board.
And then you have that internal board to board connection for the various modules.

[sandalcandal]

Kinda sounds like it might not be a real high speed ADC measurement, but more of an implied result based on comparator threshold measurements maybe?
At the claimed 12.8GHz you'd need some insanely fast ADC stuff to get a real time eye diagram. I'm not seeing that capability on that board.
And then you have that internal board to board connection for the various modules.

I don't think there's any need for a full 12.8GHz real time sampling ADC for testing signal integrity through a cable like this device is doing. Particularly since you are generating the reference signal locally; you know the exact phase and amplitude of the input to the cable. There's additionally plenty of signal processing methods which can take advantage of the fact the eye diagram isn't real-time and can be aggregated from many controlled samples over a minute (or maybe even longer).

[langwadt]

User manual here: https://www.totalphase.com/support/articles/360023273894-Advanced-Cable-Tester-v2-User-Manual
Shows screenshot the eye diagram based signal integrity check.

Seems to claim signal integrity.

http://A complete battery of tests is performed when a cable is plugged in. These tests include:

Continuity/Wiring - cable specific and customizable
DC Resistance - pin and wire measurements, Rd, Rp, Ra, and more
Signal Integrity - configurable from 518 MHz to 12.8 GHz on up to 5 differential pairs
E-Marker Verification - PD2/PD3 verification
Apple MFi Mandated Tests - Over Voltage Protection, Quiescent Current, Source Measurement Unit Tests

http://Table 10 : Signal Integrity Test Report
Data Rate   Speed of the data signal used in the test in Mbits per second
Transmit Pair   Transmitter plug and pins
Receive Pair   Receiver plug and pins
HEO   Horizontal Eye Opening is a percentage value that indicates what percentage of the reference frame of the eye is open across the widest section. The Expected is the minimum open percentage that will pass the test and is generated based on the insertion loss curve specified in the test profile. The Measured is the actual percentage open.
VEO   Vertical Eye Opening is a percentage value that indicates what percentage of the reference frame of the eye is open across the widest section. The Expected is the minimum open percentage that will pass the test and is generated based on the insertion loss curve specified in the test profile. The Measured is the actual percentage open.
Eye Image   If lock was achieved on the indicated differential pair, the eye image will be displayed. The eye image will include the mask to provide a reference for the HEO and VEO values.

If lock was not achieved, a no-lock image will be displayed.

Kinda sounds like it might not be a real high speed ADC measurement, but more of an implied result based on comparator threshold measurements maybe?
At the claimed 12.8GHz you'd need some insanely fast ADC stuff to get a real time eye diagram. I'm not seeing that capability on that board.
And then you have that internal board to board connection for the various modules.

with a repetitive signal you can use "equivalent time sampling" so only the analog frontend and sample-hold needs to be that fast

[EEVblog]

with a repetitive signal you can use "equivalent time sampling" so only the analog frontend and sample-hold needs to be that fast

Yes, but at these speeds and the need quantify a 12.5GHz signals eye diagram, ETS and the associated trigger jitter becomes problematic.
Possible of course, but again, I'm not seeing the hardware there, unless it's hidden away somewhere else.

EDIT: I presume there must be something under the metal can on the front module.

[ejeffrey]

It's true that jitter is an issue for ETS but if this is dedicated for measuring high speed links you would be able to use the clock/data recovery circuit within your receiver to provide a low jitter trigger. 

Some FPGAs have a built in eye scan capability as described here: https://wiki.analog.com/resources/tools-software/linux-software/jesd_eye_scan

Basically you run your standard CDR signal for BER testing and a second sampler with an adjustable relative delay and threshold.  Then you compare the data between them.  If it matches that is a point in the eye. This let's you build up a map of the eye   This was developed not so much to save test equipment but because for really high speed links you want to measure the eye at the FPGA input pin not on an external connector.  These days am FPGA doesn't need to be particularly beefy to support high speed transceivers although >= 20 Gb/s needed for thunderbolt are still relatively high end.

You could also use the CDR clock and a programmable delay to trigger an external ADC.  This would be a lot faster than scanning a threshold.  An ADC for ETS doesn't need to be particularly large or power hungry, and the AFE needed is rather minimal since the signal is already the correct amplitude and differential.

It's obvious the video is not intended to include a technical teardown like Dave would do and I would love to see. It's hard to tell exactly what is going on but there are definitely options besides a realtime oscilloscope that costs as much as a house.

[vaualbus]

So at the end we are sure they "cheat" in the sense that they not do BER measure but look at some other signal parameters.
But yes I agree a full teardown would be very cool!

[wraper]

So at the end we are sure they "cheat" in the sense that they not do BER measure

BER does not tell how good the cable is and how close it is to failing, only that it's crappy enough to cause data loss.