You see right at 0v, the current does move up in a straight line. It's like the LED is directly injecting a neutral charge to the surface of the entire transistor. It is like T3sl4co1l's double take on my opto-fet recommendation, then looking up the data sheet. When turned on, even in the reverse bias, each transistor should hold a predictable current curve in either polarity so long you don't exceed around 0.5v, IE significantly more than 10ma. When off, whichever transistor is in the correct direction to be open will leave too little current for the opposing transistor to even exceed the 0.7v point where that 'off' transistor begins to act like a diode and begins to conduct.
Hmm, there might be some similarity involved; I don't know what structures are used for optoFETs, offhand.
Oh hey, a citation just from next door:
https://www.eevblog.com/forum/metrology/measurements-of-leakage-current-and-offset-voltage-on-some-optofets-and-relays/with the attached PDF being quite relevant,
https://www.eevblog.com/forum/metrology/measurements-of-leakage-current-and-offset-voltage-on-some-optofets-and-relays/?action=dlattach;attach=904220GE original part; oh hey, that explains the letter-numbers-letter-number schema?
They don't really discuss construction at all though. The interdigitated pattern makes sense, but I wonder what the substrate and contact dopings, patternings or connections are. Or, conversely, do CdS photocells ever saturate [FET current saturation]? It must be at quite high voltages given their long channel length, and have been used at mains voltage (not that they're necessarily still ohmic in those applications).
Hmm, not finding any likely patent references. Keywords too generic. Will need more searching.
The effect of the phototransistor is easy to understand with normal BJT theory at least -- the photocurrent is deposited in the B-E junction (at the surface), and simply forward-biases it. The C-E or E-C path therefore conducts as any transistor in saturation does; Vce(sat) at low currents can be quite small voltages (10s mV). Which isn't resolved on the above plot (which also appears to have smoothing added, look at that "overshoot" for 5mA heh) but will be visible under zoom. And is roughly symmetrical around zero, give or take some offset, and some kink as the Rce(on) may not be linear.
Probably the inverted hFE is awful, as is usually the case for planar BJTs, maybe worse due to the optical optimizations used, unsure; I could test a 4N35 to hand and see. Could also be better.
Might also be worse for another mechanical reason, that E-B is being reverse-biased, meanwhile less charge diffuses into the C-B junction where it would cause multiplication; it may be that the curve simply ends at low currents, basically the photocurrent is shunted to the emitter without hFE multiplication taking place. Put another way, it's operated as a photodiode.
In any case, easy to test
Tim