6502 cpu was used is the nes were i cut my teeth buggering around with assembler.
6502 is an 8-bit microprocessor has 3510 transistors on a die size of 21 mm² . Has a clock speed typical of 1-2Mhz slow for its day but competitive to its counterparts despite them running at faster clock speeds thanks to its simplistic design of its state machine implomented by combinatorial logic. Its not sequenced microcode like modern cpu design like most in it era it uses PLA which makes up 15% on the chips die.
A programmable logic array is a kind of programmable logic device used to implement combinational logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output. This layout allows for a large number of logic functions to be synthesized in the sum of products (and sometimes product of sums) canonical forms. The 6502 used this to instruction decoding and sequencing. The asynchronous design of the 6502 meant 50% of its clock cycle was available for memory access this was critical at a time affordable memory had access times of 400ns. The 6502 was linguistically engineered and efficiently manufactured and cheep a very important factor in its success.
Has very few registers its registers included a 8bit wide accumulator register. Two 8 bit wide index registers. 8 bit wide status register. One 8 bit stack pointer and a 16 bit wide program counter. The stack address space is a hardwirered to a memory address range $0100–$01FF. Software addressed to the stack through four implied addressing modes instructions that pushed or pop the accumulator or the status register. The same subroutine calls all so using jump to subroutine JSR and return from subroutine.
Index and stack registers use several address modes similar to those found on the PDP-8 accessing memory locations 0-255 with a 8 bit address saving a cycle normally required to fetch high order byte addresses. The indirect modes are useful for array processing and other looping. With the 5/6 cycle "(indirect),y" mode, the 8-bit Y register is added to a 16-bit base address read from zero page which is located by a single byte following the opcode. The Y register is therefore an index-register in the sense that it is used to hold an actualindex (as opposed to the X register in the 6800 where a base address was directly stored and to which an immediate offset could be added). Incrementing the index register to walk the array byte-wise takes only two additional cycles. With the less frequently used "(indirect,x)" mode the effective address for the operation is found at the zero page address formed by adding the second byte of the instruction to the contents of the X register. Using the indexed modes, the zero page effectively acts as a set of up to 128 additional (though very slow) address registers.
The 6502 is capable of performing addition and subtraction in binary or binary coded decimal. Placing the CPU into BCD mode with the SED instruction results in decimal arithmetic, in which $99 + $01 would result in $00 and the carry flag being set. In binary mode (CLD), the same operation would result in $9A and the carry flag being cleared.
Want more ? Michael Steil goes through a history of decapping and decoding 6502 well worth a watch.
(better than watching football)
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