SCR latch-up does not happen because you run the chip at voltage somewhat higher than normal. It generally happens with large transients on I/O, like ESD discharge. Not due to running the chip at 0.15V higher than its safe maximum or exceeding its thermal limits as was with faulty BIOSes. You cannot fix an SCR latch-up susceptibility by applying a BIOS update.
A transient such as ESD is certainly not the only cause. Try to blow up a chip just from applying some power onto a chip with ill defined LV inputs

CMOS chips specify all inputs to be e.g. VCC+0.3V max. If VCC=0V, then keep everything below 300mV. I did with a FT4232H some time ago.
Modern multi-rail chips that operate near 1V still demand 3-5% tolerance, including ripple. Max may be only a few hundred mV over. 150mV is 12% of Vsoc nominal, which is a mile length. Give some latch-up path a small push, and it will be self-sufficient till something fails. I don't expect you need 700mV of an ancient 1N4148.. could be way less.
I agree you cannot fix a
susceptibility of the silicon, but you can fix the issue by enforcing a more strict SOA in e.g. BIOS or VRM firmware. That's what AMD did and their quick fix was a hard voltage cap, but I suspect there was also some sequencing timing/ramp up violation somewhere that was compounded by the high DC voltage. I also cannot say for sure what happened, but the failure mode of the CPU consuming an enormous amount of power while being "off" and then burning itself up in a runaway situation does exhibit a lot of the symptoms of a latch-up.
Anyhow, this is quite off-topic so I will leave it at that.