I'm using the
LTC4365 to protect a device powered by a 5V/2A wall wart, connected via barrel jack.
All was going well, but now the devices are in the field we're starting to see nuisance tripping. I've managed to produce the symptoms in the lab by repeatedly replugging the device's upstream facing USB port (data only, no power) into a hub. Occasionally, the act of touching the USB cable's shell to a new reference (be it a floating hub, an earthed hub, or sometimes just my fingers) will trigger the LTC4365 to disconnect.
Obviously the effect of ground shift is undesirable and trying to prevent it and keeping a more stable ground would be the ideal solution. But also, the LTC4365 seems mighty sensitive, so I'm not sure if I'm barking up the right tree here.

The LTC4365 section of the schematic looks like this. UVth = 4.51V, OVth = 5.51V and C7 provides about 5ms of droop ride-through. The nets on the left connect to the barrel jack, and the nets on the right connect to the device's 5V rail and GND. There's about 50µF of capacitance on that rail.

The USB connection looks like this.
VBUS- goes on to be direct connected to system ground.
VBUS+ is not used.

And here's my current best effort to measure the disturbance. This occurs when I connect USB to a hub. Yellow is a 10x 350MHz PVP2350 probe directly across the LTC4365's ground and UV pins. Blue is just touching the 5V rail (no dedicated reference clip). Both channels have 300MHz bandwidth set.
This is enough to cause the LTC4365 to trip, and I've confirmed through various other measurements that it is tripping ever so briefly on OV or UV.

Here's SHDN during the same event, and this time blue has its own reference.
But when I try to do the same to capture OV,
I couldn't get it to trip! It's as if the ~10pF of the probe is enough to stabilise the OV pin, even though C7 should already be doing that.

Here's the relevant part of the layout. The LTC4365 is highlighted. The barrel jack input is visible below. The dual mosfet is to the left. Red is the top layer, green is the second layer, which is a solid ground pour.

And finally, here's another view of the glitch event just for context. This time yellow is the gate pin and blue is the FAULT pin (which I've pulled with 10k).
Do you think enough noise could be coupled into the OV pin to trip the chip, even though C7 is present? Would 10pF from the probe really be enough to make a difference? I wondering whether the noise could be so high frequency to render the capacitors or resistors inductive? Am I chasing ghosts?