Most popular R, C, L values, transistor, diode etc part # (THT & SMD), and why?

[741]

I expect most people notice lots of 10k and 100n on schematics.

Loosely I suggest

• 10k is a nice in-between impedance assuming say 1-5V across it. It does not act in a floaty way as a pull-up for instance, but draws not that high a current. 100k is a bit susceptable to noise (depending what is ties to obviously).
• 100n - I'm not sure why all those de-coupling capacitors aren't say 10n...
• Inductors? No idea! It is rarely I use an inductor.

THT: Bipolar I'd use a BC846, (without too much justification). 1N4148 is the only small signal silicon in town (well the 914 too). BAT42 Schottky. THT MOSFETS are a bit rare now, so I use smd breakouts, maybe SI2302, TSM3202.

Not sure how the popularity list for resistors goes after 10k, but I'd guess a small bias towards decade values, same for capacitors.

[FreddieChopin]

Pretty good bipolar transformer is BC337, it's also very cheap in TME if thats your thing.

[Someone]

100n - I'm not sure why all those de-coupling capacitors aren't say 10n...

Or 1u? Depends on what else is needed on the board and the current market prices. Generally you have a minimum capacitance (impedance) requirement that must be met and then its all margin from there.

[T3sl4co1l]

10n actually is better suited to most general digital logic applications.  100n just ends up the default.

10k is a good compromise between speed, noise immunity, current consumption and so forth.  You'll see larger values (100k, 1M or more) in low power circuits, and smaller values in higher speed digital signals (pulls and terminators, usually under 200 ohms Thevenin equivalent*).

*For example, when you wanted to send TTL data over a ribbon cable, you'd use a bus driver to transmit, and a load termination resistor of say 330 ohms pulling up and 150 ohms pulling down; these are common values for resistor packs.  The ~100 ohm Thevenin equivalent terminates a ribbon cable (every other line a signal, the rest ground, Zo ~ 100 ohms), while the off-center voltage is suitable for the skewed thresholds of TTL (input high >2.4V, low < 0.8V; output pin driver is stronger pulling down than up).

Tim

[SparkyFX]

Not sure how the popularity list for resistors goes after 10k, but I'd guess a small bias towards decade values, same for capacitors.

Nowadays you get every value, power dissipation and tolerance in single quantities, so the quest for popularity is hard to answer, by count, by use, by cost-effectiveness? Project specific parts might trigger an order anyway.

General purpose: the whole E12 series in quantities of ~20 (i keep them in folders)... and the usual pull up/pull down values for I2C/SPI (~10kΩ ), termination for CAN/RS485 (~ 120Ω)... but the highest count is usually devoted to networks of a single matched value, should DAC/decade boxes be the type of application that you want to make, but it often makes sense real-estate-wise to use networks as part, which makes it kind of project specific.

Went with an extra stock of 1% precision decade values there.

Also nice for tinkering: SMD resistor and capacitor books.

[Someone]

10n actually is better suited to most general digital logic applications.  100n just ends up the default.

Why would 10n be "better"? Most applications see 100n and often 1u in the same package size so package/placement parasitics are not the reason. Distributing bulk capacitance is usually an overall win and savings in board space can be valuable.

[T3sl4co1l]

Exactly.  TTL and CMOS gates don't incur much charge from the supply, so about 10nF/chip is all that's needed.  Maybe a bit more on bus drivers.

Another way to look at it: by routing VCC from chip to chip (say on a 2-layer board), with caps nearby, you create a loaded transmission line structure.  If the average distance between caps is say 5cm, the stray inductance between nodes is on the order of 20-50nH.  With C = 10nF, this gives an average PDN (power distribution network) impedance of sqrt(50nH/10nF) ~= 2.3 ohms.  Which means a typical shoot-through spike of ~100mA can only develop a peak voltage drop of ~230mV, no problem out of a total 5V supply.

Lower frequencies (below 1 / (2 pi sqrt(50nH 10nF)) ~= 7MHz) are sourced through the supply wires, or less frequently placed bulk caps (which should be chosen to have comparable ESR -- 2 ohms is about typical of a 10uF electrolytic).

As you can see, rather than taking a default as given, if we ask, "okay, how much do we really need?", we also see where we can lighten up even further -- for example, CD4000 logic is even slower, lower in current consumption and higher in supply voltage, so could easily succeed without bypass caps at all, maybe just one bulk cap on a board(!).  Or if we're using 74AC or 74LVC logic or such (much higher peak currents, much faster), we should keep the distance between IC and cap very short, and consider using a larger cap, or placing them more often.  Or if we have a much more demanding load (like an FPGA or CPU core drawing load steps of some amperes, with a voltage tolerance under 100mV), we instantly know where to beef things up instead.

Tim

[SteveyG]

10n actually is better suited to most general digital logic applications.  100n just ends up the default.

Why would 10n be "better"? Most applications see 100n and often 1u in the same package size so package/placement parasitics are not the reason. Distributing bulk capacitance is usually an overall win and savings in board space can be valuable.

You'll probably find the capacitance not too dissimilar between the 10nF and 100nF in the same package size once at operating voltage.

[jfiresto]

Exactly.  TTL and CMOS gates don't incur much charge from the supply, so about 10nF/chip is all that's needed..... If we ask, "okay, how much do we really need?", we also see where we can lighten up even further -- for example, CD4000 logic is even slower, lower in current consumption and higher in supply voltage, so could easily succeed without bypass caps at all, maybe just one bulk cap on a board(!)....

I think you have got that right. For fun, I have been designing a simple device, using 4000-series CMOS, for tethering a modern digital camera for a 40+ year old stereo microscope. I thought the design should last the lifetime of the microscope, that is, for at least another 40+ years. Hence, the classic, seemingly immortal technology to use with a classic microscope.

I have to remind myself: slow edges, high noise margins – use less decoupling! I am down to one bulk and one local capacitor. I am tempted to keep the latter, as a cheap offering to appease the digital design gods.

[T3sl4co1l]

A similar lesson is that, if you're routing the same sort of circuitry over a multilayer board (with VCC/GND plane), supply pins and bypass caps act almost in unison; it doesn't much matter where they are.  You can get away with, not just a cap every few ICs, but a few caps total, in that case!  And they probably should be larger, so this would be a good place for 100n's.

Again, very low impedance supplies (VCORE etc.) need more capacitors, and capacitance, because even the low inductance of the inner planes becomes relevant at such impedances -- and frequencies (usually, on-chip bypass takes over in the 100MHz+ range, so you want a low impedance through the board up til there).

There are many other assumptions that need to be met, and a full analysis is always helpful; but the starting points are simply:
Zo <= Vripple / Istep
Zo = sqrt(L/C)
Fo = 1 / ( pi sqrt(L C))

Tim

[Someone]

10n actually is better suited to most general digital logic applications.  100n just ends up the default.

Why would 10n be "better"? Most applications see 100n and often 1u in the same package size so package/placement parasitics are not the reason. Distributing bulk capacitance is usually an overall win and savings in board space can be valuable.

You'll probably find the capacitance not too dissimilar between the 10nF and 100nF in the same package size once at operating voltage.

Or we might find you've got no idea what you're talking about? Taking the cheapest 0402 (1005) parts in stock on digikey that had their full data conveniently available we can see that in realistic use cases that does not occur. The 100nF was actually the cheapest and not even half the price of the 1uF part hence the above discussion of why small capacitors are not the best choice. Engineering is many dimensional and can't be reduced to simple dot points.

[SteveyG]

10n actually is better suited to most general digital logic applications.  100n just ends up the default.

Why would 10n be "better"? Most applications see 100n and often 1u in the same package size so package/placement parasitics are not the reason. Distributing bulk capacitance is usually an overall win and savings in board space can be valuable.

You'll probably find the capacitance not too dissimilar between the 10nF and 100nF in the same package size once at operating voltage.

Or we might find you've got no idea what you're talking about? Taking the cheapest 0402 (1005) parts in stock on digikey that had their full data conveniently available we can see that in realistic use cases that does not occur. The 100nF was actually the cheapest and not even half the price of the 1uF part hence the above discussion of why small capacitors are not the best choice. Engineering is many dimensional and can't be reduced to simple dot points.

That graph is the DC bias curve, but bypassing is not DC. Once you look at operating frequency the capacitor behaves quite differently and the dielectric thickness of the capacitor layers plays a much larger effect.

[Someone]

10n actually is better suited to most general digital logic applications.  100n just ends up the default.

Why would 10n be "better"? Most applications see 100n and often 1u in the same package size so package/placement parasitics are not the reason. Distributing bulk capacitance is usually an overall win and savings in board space can be valuable.

You'll probably find the capacitance not too dissimilar between the 10nF and 100nF in the same package size once at operating voltage.

Or we might find you've got no idea what you're talking about? Taking the cheapest 0402 (1005) parts in stock on digikey that had their full data conveniently available we can see that in realistic use cases that does not occur. The 100nF was actually the cheapest and not even half the price of the 1uF part hence the above discussion of why small capacitors are not the best choice. Engineering is many dimensional and can't be reduced to simple dot points.

That graph looks to be for DC. What frequency are you assuming for bypass purposes?

How about you find the data to show what you think is occurring? Since they are all in the same package size there is almost no difference in the parasitics, their |Z| plots above resonance all follow the same path. But if you are thinking larger AC effects, its a bypass cap, you don't want a significant AC component on it!

You're adding another short and hollow comment that doesn't stand up to scrutiny.

[T3sl4co1l]

Yes, noteworthy that ESL is basically package size.  So you get the same bypassing effect from 10n as 10u, in say 0603 size, at frequencies high enough that ESL dominates.

Tim

[SteveyG]

10n actually is better suited to most general digital logic applications.  100n just ends up the default.

Why would 10n be "better"? Most applications see 100n and often 1u in the same package size so package/placement parasitics are not the reason. Distributing bulk capacitance is usually an overall win and savings in board space can be valuable.

You'll probably find the capacitance not too dissimilar between the 10nF and 100nF in the same package size once at operating voltage.

Or we might find you've got no idea what you're talking about? Taking the cheapest 0402 (1005) parts in stock on digikey that had their full data conveniently available we can see that in realistic use cases that does not occur. The 100nF was actually the cheapest and not even half the price of the 1uF part hence the above discussion of why small capacitors are not the best choice. Engineering is many dimensional and can't be reduced to simple dot points.

That graph looks to be for DC. What frequency are you assuming for bypass purposes?

How about you find the data to show what you think is occurring? Since they are all in the same package size there is almost no difference in the parasitics, their |Z| plots above resonance all follow the same path. But if you are thinking larger AC effects, its a bypass cap, you don't want a significant AC component on it!

You're adding another short and hollow comment that doesn't stand up to scrutiny.

I think you're missing the point of bypass capacitors. The AC component of concern is that created by the switching logic.

The parasitics are very different between capacitor values for a fixed overall size. The increase in capacitance is exchanged for different layer thicknesses and layer counts.

[tszaboo]

You mostly end up with 1K and 10K or 470 and 4.7K resistors. Because 4,7 is almost 5.
For capacitors, 80% that I use is mostly 100nF. And bigger values next to power supplies, which are carefully selected.

But then again, when working with precision DC stuff, I place E192 series 0,1% resistors without thinking about it twice.

[Someone]

10n actually is better suited to most general digital logic applications.  100n just ends up the default.

Why would 10n be "better"? Most applications see 100n and often 1u in the same package size so package/placement parasitics are not the reason. Distributing bulk capacitance is usually an overall win and savings in board space can be valuable.

You'll probably find the capacitance not too dissimilar between the 10nF and 100nF in the same package size once at operating voltage.

Or we might find you've got no idea what you're talking about? Taking the cheapest 0402 (1005) parts in stock on digikey that had their full data conveniently available we can see that in realistic use cases that does not occur. The 100nF was actually the cheapest and not even half the price of the 1uF part hence the above discussion of why small capacitors are not the best choice. Engineering is many dimensional and can't be reduced to simple dot points.

That graph looks to be for DC. What frequency are you assuming for bypass purposes?

How about you find the data to show what you think is occurring? Since they are all in the same package size there is almost no difference in the parasitics, their |Z| plots above resonance all follow the same path. But if you are thinking larger AC effects, its a bypass cap, you don't want a significant AC component on it!

You're adding another short and hollow comment that doesn't stand up to scrutiny.

I think you're missing the point of bypass capacitors. The AC component of concern is that created by the switching logic.

The parasitics are very different between capacitor values for a fixed overall size. The increase in capacitance is exchanged for different layer thicknesses and layer counts.

The data is out there and readily available, why can't you provide any examples? We can take a look at the |Z| and see they are almost identical. You really need to research your points because they are untrue every single time.

[ogden]

A similar lesson is that, if you're routing the same sort of circuitry over a multilayer board (with VCC/GND plane), supply pins and bypass caps act almost in unison; it doesn't much matter where they are.  You can get away with, not just a cap every few ICs, but a few caps total, in that case!  And they probably should be larger, so this would be a good place for 100n's.

Again - it depends. You could easily find network of decoupling capacitors like 4x1uF (0805) + 10x100n (0603) + 20x10n (0402) around/under single ASIC or FPGA.

[Someone]

A similar lesson is that, if you're routing the same sort of circuitry over a multilayer board (with VCC/GND plane), supply pins and bypass caps act almost in unison; it doesn't much matter where they are.  You can get away with, not just a cap every few ICs, but a few caps total, in that case!  And they probably should be larger, so this would be a good place for 100n's.

Again - it depends. You could easily find network of decoupling capacitors like 4x1uF (0805) + 10x100n (0603) + 20x10n (0402) around/under single ASIC or FPGA.

That was the practice 15-20 years ago:
https://www.xilinx.com/support/documentation/application_notes/xapp623.pdf
Why put in 0402 10n when its cheaper to use 100n or 1u in the same footprint?

[T3sl4co1l]

Seems to me, most cases of graded values/sizes are erroneous -- appnotes mention it, but don't instruct one to perform an analysis.  So you often see rows of caps on pins that don't need them, and that end up making things worse (higher peak |Z| at some frequency) rather than better.

One hopes that, say, cellphone or PC or GPU designers have the tools to perform this analysis, and justify their layout accordingly.  One-off users of FPGAs, CPUs, etc., I wouldn't share the same hope for, and default to the above skepticism instead.

Note that location doesn't matter so much as distribution.  For an FPGA/CPU, it's more important that the caps are distributed along the PDN, lowering its network impedance overall, and keeping the Q low; just putting a wad of caps at the supply, and another at the load, makes a dumbbell structure prone to resonance.  Which types/sizes of caps are used in the respective locations, depends.

In any case, smaller sizes are preferred for lower ESL, if nothing else.  The ESL is essentially length.

And as always, it really doesn't matter for noncritical purposes.  If you aren't using every last MHz of every last gate in the FPGA, and you aren't handling highly reliable (BER < 1e-9 say?) or extremely precise (jitter << 1ps?) data, you aren't going to notice the difference, at least unless it's so grossly bad as to fail even then.

Tim

[ogden]

A similar lesson is that, if you're routing the same sort of circuitry over a multilayer board (with VCC/GND plane), supply pins and bypass caps act almost in unison; it doesn't much matter where they are.  You can get away with, not just a cap every few ICs, but a few caps total, in that case!  And they probably should be larger, so this would be a good place for 100n's.

Again - it depends. You could easily find network of decoupling capacitors like 4x1uF (0805) + 10x100n (0603) + 20x10n (0402) around/under single ASIC or FPGA.

That was the practice 15-20 years ago:
https://www.xilinx.com/support/documentation/application_notes/xapp623.pdf
Why put in 0402 10n when its cheaper to use 100n or 1u in the same footprint?

Yes indeed modern approach is to use bigger values. Smallest I see is 0.47uF (attach, note that FPGA usually have many I/O banks). You guys were talking about 40 year old practice of discrete logic decoupling, I thought mentioning huge numbers of 10n caps would be appropriate
[edit] BTW that Xilinx article explains decoupling theory in greater details.

One-off users of FPGAs, CPUs, etc., I wouldn't share the same hope for, and default to the above skepticism instead.

One-off users may refer to application notes, copy/paste from reference design or consult FAE (field application engineer) of IC manufacturer.

[SteveyG]

The data is out there and readily available, why can't you provide any examples? We can take a look at the |Z| and see they are almost identical. You really need to research your points because they are untrue every single time.

Your graph shows quite a difference   

A quick search on Farnell for Kemet and muRata capacitors shows 1nF ~£0.0308, 10nF ~£0.0397, 100nF at £0.0315 but reduced reduced voltage and 1uF as £0.0784 but only 4WV in 0402. Recent testing with a HP vector impedance analyser showed the capacitance of a small 1uF 0603 is no where near 1uF at 3.3V. We had to come up with an alternative arrangement for one of the medical implementations.

Not sure if we're talking at cross purposes or something. What do you think the trade-off is in terms of capacitance and size? As you know, you don't get anything for free and the 10nF capacitors aren't filled with air for the other 990nF.

[ogden]

What do you think the trade-off is in terms of capacitance and size?

Let me guess. Voltage?

[Someone]

The data is out there and readily available, why can't you provide any examples? We can take a look at the |Z| and see they are almost identical. You really need to research your points because they are untrue every single time.

Your graph shows quite a difference   

A quick search on Farnell for Kemet and muRata capacitors shows 1nF ~£0.0308, 10nF ~£0.0397, 100nF at £0.0315 but reduced reduced voltage and 1uF as £0.0784 but only 4WV in 0402. Recent testing with a HP vector impedance analyser showed the capacitance of a small 1uF 0603 is no where near 1uF at 3.3V. We had to come up with an alternative arrangement for one of the medical implementations.

A) The graphs all show the 1uF example being superior, even above resonance. The capacitance drops with working voltage but again, the graphs and experiments show the 1uF still has more capacitance than the 100n or 10n, it may have lost 50% but it was 1,000% or 10,000% bigger to begin with.

You might be able to cherry pick some corner cases where a very poor 1uF 0402 part is inferior (as pictured below) but the commodity/bulk/budget parts coming off the lines right now for designs today are far superior to your fixed mental model. 0603 was the optimal package 15-20 years ago, times change.

B) Pricing on obsolete components (at single quantities?) at farnell is not where the market is at right now. These are commodities you buy by the reel full from brokers/distributors rather than retail/MRO suppliers.

Part parasitics and price are only half the story, they need to be mounted in the circuit which then adds on to both of those characteristics.

[T3sl4co1l]

You are comparing two different things.

Impedance curve is measured at zero bias.

Capacitance drops markedly under bias.

Therefore the impedance curve shifts in real use, and will be generally somewhere above and to the right of the published curve.

It's not obvious if the ESL should change much: it can, because this is defined by the apparent surface where current flows.  In a hi-K capacitor, skin effect dominates, and the surface is close to the outside (similar to the ESL of a solid metal chip of the same size).  At lower K, current diffuses into more of the capacitor, and ESL is higher.  This will vary with bias, so the curve will be generally above what's published, but by how much is not clear.

Put another way: you're varying the rho of the capacitor, and thus the skin depth.  It doesn't matter that rho in this case is negative imaginary (capacitive): that affects the propagation characteristics (it's not 100% dissipative with depth), but not the length constant associated with skin effect (give or take a factor of pi and such).

I suppose it's noteworthy that skin effect varies ESL regardless, and this is simply a frequency- and resistivity-dependent effect.  The contribution to ESL is most significant at low frequencies, but it may be that a typical case has the impedance valley well above the point where skin effect is already negligible, and so this argument isn't relevant.

Tim