Physical Construction Techniques of Point-Contact and BJT's

[beaker353]

I'm working on a research'ish paper for my college Solid State I class.  The assigned subject was transistors; past, present, and future.  If so desired, we are able to limit the scope of the paper to a given area.  I chose to limit my paper on the physical construction of point-contact and BJTs. I'm finding quite a bit of information on early point-contact designs as well as emerging technologies for faster, more efficient designs for the future. 

One area I am struggling to find information that isn't miles over my head is current day manufacturing/construction techniques. The information seems to either be very basic theory (like the basic PNP theoretical model we have all seen in textbooks), or some really high level multilevel stuff in super fast FPGAs or modern processors. I'm looking for more along the lines of what I would find in a 2N2222 I got out of the lab supply drawer if I could pull out the die and look at how it was constructed and why.

For example, I found some information below that describes a silicon fabrication process to create a transistor (line type drawing). Pretty basic information, but it's kinda what I'm looking for.  However, when I run across die photos like below, I see all types of strange shapes that I'm not 100% sure what I'm looking at (attached photo). Is the idea to increase the depletion zones surface area to increase current carrying capability or does this somehow relate to the transistor beta? I'm having trouble find this level of not basic, but not advanced, information.

I am by no means asking for you guys to do my work for me. Just maybe a bit of guidance where I should be looking for my information.  Thanks!

-EM

[SeanB]

Hard to find die pics, though i have a whole load of Motorola databooks ( remember those) which have the pages with the different die shapes in it.

That is a 2N3055/2N3773 which has the fingers. They are there to increase the active area, as the junction is formed between the edges of the base and emitter junctions (emitter to the middle of the die, left pin in photo. Base is the outer side, top pin in photo. Collector is to the bottom and in this unit the case) so you either have a long die, which has problems with the current flow along the long surface differing along the device unless you place multiple bond wires ( used in RF power devices to reduce capacitance and lead inductance) or you fold it into the fingers that you have here. This allows a single cheap bond wire to handle a high current.