"Please Rate my Design/Schematic"... [RANT]

[Benta]

I think it's great when noobs ask for feedback on their creations. And I (mostly) help.
But unfortunately there's a trend towards unreadable schematics, fed by some blathering idiots with web sites, and apparently supported by some web-based EDA. IDK.

Fashion seems to be putting every part in a little box and placing a label on each pin to connect the little boxes. It looks neat, like stacking shoe cartons.... and it's completely undecipherable.
Labels everywhere... where does this label connect... did I find all labels in a net... which are output and which input... etc. etc.

I did a little exercise to demonstrate my point. I took an existing schematic of mine and redrew it in the "modern" way. Quite at lot of work, inventing label names and typing them, plus drawing all the little boxes etc.

I attach my "modern" schematic. Comments appreciated.

Tomorrow I'll post the original schematic for comparison. If you like a challenge, tell me what this "modern" schematic/circuit does.

[/RANT]

PS1: I added a bit of colour, it's the festive season.
PS2: The real hard-core "modernists" would have used DIP-14/16 graphics for symbols. I kept the real ones, no reason to exaggerate.

[temperance]

I really like it. I don't want to be over critical but you could use more colors. You are clearly a fan of blue. You also forgot draw a box around all the boxes because page borders are for people without imagination. But the overall look and feel is about right except for the yellow around the input which is hard to see.

I don't know what it does apart from flipping and counting something because I feel that the level of detail is still too high. IC's are supposed to be boxes with pin numbers only and when possible should be rotated sideways. But that's of course only for true masters. But if you want to become really good at it, I can also suggest the usage of boxes around boxes to group component into more functional groups. Functional groups must of course be drawn with a different line width.

[amyk]

The people who do that seem to be emulating some commercial schematics, which are in the same "disconnected parts floating in boxes" style. It's not a particularly new phenomenon either - see attached example from mid-2000s.

[pcprogrammer]

I absolutely see your point in this and drawing a clock divider this way is indeed ridiculous.

What makes this one even worse is the usage of net names instead of labels. A label has a pointed box around the name. In the old days (Orcad) the point of the label was an indication of the direction of the signal, or bus and a two pointed one was used to indicate being bidirectional, like a databus.

But there are schematics that need a mixture of the techniques. Instead of drawing boxes to separate functionality or to indicate what a part is for, using separated sheets is better. Like a sheet for the processor part, and one for the power supply, one for the video controller, etc. To make the connections across the sheets you need labels.

On a single sheet it sometimes makes it so cluttered trying to connect everything with single wires, that labels can be the solution to clear things up. Or maybe a bus can be used to connect parts of the schematic, but having mixed types of signals on the bus can also be confusing. Like putting memory control signals on the databus.

It of course also depends on the intent of the schematic. If it is just for personal use to get to an error checked PCB, who gives a f***. When the intention is it to be for service and has to be read by a wider audience, than yes, you better make sure it is a good readable schematic. But there is a learning curve, and with new technology come new methods and options.

I myself also am going through a (re)learning curve, as to what is the best in drawing schematics, and try to find the benefits of both worlds.

A carefully balanced mix could be used in my opinion.

[forrestc]

Your circuit will never reload the preset since you don't have power for U4.   Plus you didn't draw a thousand caps in the power box.

I'm a big fan of something in-between.   Following lines on a schematic which has every single line connecting everything is just as bad as this other extreme.  I'd rather see a 'traditional' schematic for each functional chunk and then the interconnects be done similar to the new style.

For example, It's perfectly ok to see a CPU on page one and connect all it's pins to labeled nets on busses, and then have various things which connect to that bus just refer to the bus symbol.  I.E. have memory on a memory page.  Or have an 'analogbus' which all of the ADC inputs and the sources connect to in two different spots.   

I'm guessing this has happened due to the need to break apart schematics for complex systems so each chunk is understandable - but a single component doesn't equal a chunk.   Unless it's a 400 pin CPU.

What is even worse is when they start breaking apart components - i.e. 'counter 2 outputs' is in one spot and 'counter 2 inputs' are in another and 'counter 2 control pins' are in a third.   

[Brumby]

A computer may have no problems with it.  AI may love it.  Humans ... not at all.

To be blunt, it's simply not "readable".

Perhaps I'm just a grumpy old sod - but I like the left-to-right functional sequence that exists on the vast majority of the circuits I have in my library, references and other resources.

[2N3055]

You are missing overly complicated artsy fartsy logo of the maker, that one spent 10x more time to draw that the schematic itself.

[Brumby]

You are missing overly complicated artsy fartsy logo of the maker, that one spent 10x more time to draw that the schematic itself.

I'm laughing (on the inside).

Sometimes absurdities like that are all too real.

[Wolfram]

It's a solid effort but you missed an opportunity by using clear and standardized symbols for the logic functions. Drawing the chip as a block, with the pins in order, can do wonders for illegibility. Pin names are optional. This works especially well in op-amp circuits, using dual or quad parts. Makes even the most basic and well known circuit topologies unrecognizable without redrawing them from scratch.

[tggzzz]

It's a solid effort but you missed an opportunity by using clear and standardized symbols for the logic functions. Drawing the chip as a block, with the pins in order, can do wonders for illegibility. Pin names are optional. This works especially well in op-amp circuits, using dual or quad parts. Makes even the most basic and well known circuit topologies unrecognizable without redrawing them from scratch.

Better: just copy a PCB layout symbol, and insert signal names. Makes it easier to put on a solderless breadboard or strip board.

In addition those colours are too strong and distinct: modern fashion is for dark grey on a light grey background, or light yellow on a dark yellow background. Benefit: nobody will (be able to) print it out, thus making it easier to issue new documents.

In addition make sure vital information is conveyed only in the colour; you'll be able to see it, and tough luck to the ~8% of men (<1 % women) who are colour blind.

[Bud]

For better unreadability add 100 resistors and capacitors individually boxed and Net Named.

[Benta]

It's a solid effort but you missed an opportunity by using clear and standardized symbols for the logic functions. Drawing the chip as a block, with the pins in order, can do wonders for illegibility. Pin names are optional. This works especially well in op-amp circuits, using dual or quad parts. Makes even the most basic and well known circuit topologies unrecognizable without redrawing them from scratch.

Hahaha!
I did mention drawing them as Dip-14 or DIP-16, though.

[temperance]

You are missing overly complicated artsy fartsy logo of the maker, that one spent 10x more time to draw that the schematic itself.

Which must be replicated in the solder mask at all cost. Preferably in colour.

[ebastler]

For (large) microcontrollers or FPGAs, where most pins have somewhat generic and configurable functionality, I think it is fine to draw them with just wire stubs and signal labels on most pins. Trying to actually draw connecting lines to all peripherals would create a huge mess. I tend to draw only some functions on dedicated pins -- crystal, reset button, boot config switch etc. -- connected directly to these large ICs.

(But then, don't name the signals "GPIO27" or such. Give them descriptive names!)

I prefer to draw direct connections within circuits built from multiple smaller chips, where the chip pins serve dedicated, hardwired functions.

[2N3055]

You are missing overly complicated artsy fartsy logo of the maker, that one spent 10x more time to draw that the schematic itself.

Which must be replicated in the solder mask at all cost. Preferably in colour.

Don't forget to color coordinate silkscreen and solder mask, and unnecessary gold plating.

[Nominal Animal]

😳

^{(Click to embiggen)}
😢

[tggzzz]

Excellent (not!) pin description for the ATTiny85. Forgot about that "style".

I think the isolated R1/10k technique has been mentioned elsewhere.

[Nominal Animal]

Excellent (not!) pin description for the ATTiny85. Forgot about that "style".

In my defense, I didn't draw it myself; it's what EasyEda provides for ATtiny85-20PU.  Should've drawn my own; I hate those extra-long pin descriptions.

Symbol colors (including pin legs) cannot be changed except by creating a copy of the symbol.  All symbols are public and discoverable.  Wire colors are my fault; they default to green.  I use red for power rails and black for grounds.  In this one, green indicates max. 12V signals, blue max. 5V signals.

Both the single and dual 12V PWM fan controllers using ATtiny85 are my own designs, about a year ago.  I'm still learning.

I think the isolated R1/10k technique has been mentioned elsewhere.

I originally had a reset button there, but I realized it wasn't needed, so simplified to a single pull-up resistor instead.  Should've moved it, though.

Also, R6 should really be on the +5V side instead of the wiper.  It's purpose is to ensure an accidental short between any of the three pins is not dangerous, because the pot is remote, connected using a 3-pin JST PH2.0 connector.

So, it's partially an issue with the symbols LCSC has provided for EasyEda, and partially newbies like myself trying to create modular, easily modified schematics.  It's not about trying to be annoying; we just don't know how to do better, yet!

Besides, now you know exactly how Linux developers feel when long-time Windows users are asking why doing X in Linux is so hard, what is the best program to replace Y, and why nothing makes much sense in Linux. 

"Until you old hands change your attitude towards us newbies, schematic capture and EE as a hobby will not be as popular as social media."

[Benta]

In my defense, I didn't draw it myself; it's what EasyEda provides for ATtiny85-20PU.  Should've drawn my own; I hate those extra-long pin descriptions.

Interesting. I've long suspected that EasyEDA is the instigator, but never got around to testing it.

[pcprogrammer]

In my defense, I didn't draw it myself; it's what EasyEda provides for ATtiny85-20PU.  Should've drawn my own; I hate those extra-long pin descriptions.

Which is very easy to do in EasyEda. 

As it is very open and everybody can add parts to it, I tend to make most parts myself to make sure they match what I want. Also for PCB footprints, I won't sent a design to a fab unless I checked it against the components by laser printing the design and see if the parts align and fit.

For professionals it probably makes more sense to use something offline and with more features for special stuff, but for a hobbyist it works like a charm as long as you check everything, just like with all that is presented on the internet.

[tggzzz]

Excellent (not!) pin description for the ATTiny85. Forgot about that "style".

In my defense, I didn't draw it myself; it's what EasyEda provides for ATtiny85-20PU.  Should've drawn my own; I hate those extra-long pin descriptions.

I would have deleted all the irrelevant possible uses of each pin. If it being used as MISO, then it cannot also be AIN1.

Symbol colors (including pin legs) cannot be changed except by creating a copy of the symbol.  All symbols are public and discoverable.  Wire colors are my fault; they default to green.  I use red for power rails and black for grounds.  In this one, green indicates max. 12V signals, blue max. 5V signals.

I wouldn't argue against that, provided they show legibly on a black/white print, and colour blind people aren't grossly disadvantaged.

I think the isolated R1/10k technique has been mentioned elsewhere.

I originally had a reset button there, but I realized it wasn't needed, so simplified to a single pull-up resistor instead.  Should've moved it, though.

Also, R6 should really be on the +5V side instead of the wiper.  It's purpose is to ensure an accidental short between any of the three pins is not dangerous, because the pot is remote, connected using a 3-pin JST PH2.0 connector.

So, it's partially an issue with the symbols LCSC has provided for EasyEda, and partially newbies like myself trying to create modular, easily modified schematics.  It's not about trying to be annoying; we just don't know how to do better, yet!

Using EasyEDA isn't an excuse

In my experience, which includes keyboard-only-no-mouse ORCAD in the 80s, modifying schematics isn't hard. It requires a little mental pre-planning, much less thought that is required to create and create a circuit and schematic.

Besides, now you know exactly how Linux developers feel when long-time Windows users are asking why doing X in Linux is so hard, what is the best program to replace Y, and why nothing makes much sense in Linux. 

Windows users have to be much cleverer and more adaptable than me, simply because they are using Windows. I'm not clever enough to run Windows safely, and the GUI and applications seem to radically change every 5 years - usually for the worse.

Having said that, there are some Win3.11 dialogs still to be found in Win11 (ODBC setup).

[themadhippy]

I've long suspected that EasyEDA is the instigator

As with most software siso applies

[hwasti]

It's not a particularly new phenomenon either - see attached example from mid-2000s.

They were not sending the best and the brightest to be apps engineers back then either.

In fact, many of the worst counterproductive design elements are created by application designs. Separate ground plane and guard traces to prevent cross talk are the top two.

[Nominal Animal]

Which is very easy to do in EasyEda. 

Yes – see documentation example (HTML guide).

Footprints, too, although there is a recommended naming rules (PDF), since they are all visible to other users.  The naming of the footprints is really the hardest part...

I would have deleted all the irrelevant possible uses of each pin. If it being used as MISO, then it cannot also be AIN1.

That requires editing the symbol, essentially making your own private copy of it.  The pin name texts are not editable in the EasyEda schematic editor, only in the symbol editor.  It is less work to just redraw ones own symbol, and I do often do, both symbols and footprints.

For resistors and capacitors, I use my own 0603+0805 footprints: the outline is the same as the standard 0805, but the gap is the same as 0603.

Using EasyEDA isn't an excuse

I didn't intend any of it as such; only as an explanation.

I am a bit distressed that so many members feel so strongly about the failures.  You see, in another thread, I tried drawing a better version of this analog video switch schematic,

^{(Click to embiggen)}

but routing the wires in the schematic was hard; I tried a couple of component layouts, but they all became spaghetti. Again, colors indicate signal type (blue is analog, cyan is digital, green is almost-DC –– except for EXTCLOCK, which either isn't used or is 32 MHz).  The switch in lower left corner selects between the CN2 and CN3 output, and whether CN3 gets the color signal, or the monochrome signal, both cases via attenuation resistors.  Input signal amplitude is a bit higher than the 0.7Vpp VGA expects so R1-R6 are To Be Determined in practice, perhaps using trimpots.  (VGA analog video signals are terminated at the display device, 75Ω to ground.)  All digital signals use 5V TTL level logic.

Because of this, I do claim that this kind of splitting is done because properly connecting the wires is way harder (without creating an even more horrible mess), when you don't have the experience yet in placing the components so the wires fall at least halfway neatly.  Using net labels like I have here is simpler; I just didn't know how deeply annoying this is to more experienced people.

Noted.  Will try harder in the future. 

[tggzzz]

I would have deleted all the irrelevant possible uses of each pin. If it being used as MISO, then it cannot also be AIN1.

That requires editing the symbol, essentially making your own private copy of it.  The pin name texts are not editable in the EasyEda schematic editor, only in the symbol editor.  It is less work to just redraw ones own symbol, and I do often do, both symbols and footprints.

Copy or duplication is required in all EDA tools, simply because the use of the pins is specific to your design. Hence, if one EDA tool doesn't make that easy, avoid that tool and use another.

The software equivalent is to copy-paste something from the web without ensuring it fits your program Sure, a lot of web-weenies do that - and look at the mess we all have to endure.

...
but routing the wires in the schematic was hard; I tried a couple of component layouts, but they all became spaghetti.

It does tend to, but over the many decades techniques have been developed to contain the issue. Nonetheless care and good taste are required.

The very rough software equivalent is not bothering to indent code to indicate structure. (Mind you some scrotty little languages rely on tab and space having different semantics. Other popular languages use spaces to indicate meaning)

Again, colors indicate signal type (blue is analog, cyan is digital, green is almost-DC –– except for EXTCLOCK, which either isn't used or is 32 MHz). 

Is that just your convention, or the tool convention - and how is a new reader meant to know that?

Because of this, I do claim that this kind of splitting is done because properly connecting the wires is way harder (without creating an even more horrible mess), when you don't have the experience yet in placing the components so the wires fall at least halfway neatly.  Using net labels like I have here is simpler; I just didn't know how deeply annoying this is to more experienced people.

The software equivalent is code using "goto name", instead of if-the-else, while, exceptions. That has been deprecated for half a century.