Google will make your own chips for free

[RoGeorge]

https://www.electronicsweekly.com/news/business/free-chips-2020-07/


or, if you don't have time for a 95 minutes video, here are the slides only.

 

[jmelson]

Hmmm, we have had chips made through MOSIS and now Europractice, in a shared-project wafer mode.  NOT at all cheap, a 5 x 7 mm chip in a relatively modest technology runs about US $40K without packaging, for a very short run of, say, 160 die.  While I can see some subsidized projects that are interesting to the provider of the subsidy, no WAY will they fabricate any and all projects for free.

Jon

[mian2zi3]

I watched the video.  They are aiming to do a multi-project wafer with 40 projects every 3 months.  If they get more than 40 projects, they decide on a selection criteria (he mentioned lottery as one option).  Projects get 10mm^2 of silicon and deliver ~100 chips (packaged).

[Bud]

An obvious question: what is in it for Google? Are they looking to gain experience in IC manufacturing? Are they looking to create a market place and be in control that manufacturing? Are they looking to scrape information on what is of interest to engineers? Else?

[RoGeorge]

They are working on an open source EDA tools for chips design.  It is almost ready and they need to test it, and they'll also need to build a user base familiar with the new tools.

They can run test and then debug the chips by themselves, or they can do what they are doing now, where everybody benefits.  They told in the video to consider your project as open source and disposable, so it might or it might not work, but I think it is still a very good deal for the beta testers.

[DC1MC]

Somebody should design a superl-LTZ1000 reference, with an on-chip heater, 50 diodes in parallel and a buffer .

 Cheers,
 DC1MC

[Weston]

I think you are under estimating the money that google can just throw around (and write off as R&D type expenses...).

The cheapest shared project wafer service nowdays is ~$5k for a small IC and the process node is relatively old, so I don't think google is throwing absolutely massive amounts of money at this or anything.

IC design is really hard to get experience in and all of the tooling is closed source and really expensive. Getting access to the cell libraries alone requires NDAs. Google is most likely trying to build up a community around open source hardware design / IC design which will help in the talent pool, benefiting their own recruiting in the future. Companies fund PhD students all the time and get relatively little out of it, I would not be surprised if they got a greater return for their dollar in terms of talent development / recruiting with this.

I have been wanting to get into IC design for a while now, but my own research group does not do work in the area. Free is a nice price to try something out, so I have been following this closely. Anything I do is going to require the analog cell libraries though, which they have not released yet.

[Bud]

Having worked for mid to big size companies i can hardly see "where everyone benefits" being a motivation for businesses.

[mian2zi3]

An obvious question: what is in it for Google?

Tim addresses this directly in the video: https://youtu.be/EczW2IWdnOM?t=407.  Google wants to create an open, innovative ecosystem for silicon so it will be easier for them to build accelerators for their workloads to meet the growing demand for compute. TPU is only one example of the kind of accelerators they want to build.

[amyk]

Hmmm, we have had chips made through MOSIS and now Europractice, in a shared-project wafer mode.  NOT at all cheap, a 5 x 7 mm chip in a relatively modest technology runs about US $40K without packaging, for a very short run of, say, 160 die.  While I can see some subsidized projects that are interesting to the provider of the subsidy, no WAY will they fabricate any and all projects for free.

Jon

That's 35mm^2, which is pretty big for an IC. Many MCUs are smaller than that, as evidenced by the size of the packages they come in.

[jmelson]

Hmmm, we have had chips made through MOSIS and now Europractice, in a shared-project wafer mode.  NOT at all cheap, a 5 x 7 mm chip in a relatively modest technology runs about US $40K without packaging, for a very short run of, say, 160 die.  While I can see some subsidized projects that are interesting to the provider of the subsidy, no WAY will they fabricate any and all projects for free.

Jon

That's 35mm^2, which is pretty big for an IC. Many MCUs are smaller than that, as evidenced by the size of the packages they come in.

Yes, our stuff is mxed-signal, but 90% of the area is analog, with some great big transistors for noise, and big capacitors to store charge until the result is read out.  So, no, they aren't small.

Jon

[magic]

An obvious question: what is in it for Google? Are they looking to gain experience in IC manufacturing? Are they looking to create a market place and be in control that manufacturing? Are they looking to scrape information on what is of interest to engineers? Else?

We are just giving free shit away, why are you asking questions like some conspiracy theorist, comrade?

No idea. Maybe it's for the development of their design package which they may want to use internally for their future chip projects. Having briefly worked at a company that supplied stuff to Google, I can assure you that they absolutely loathe being dependent on (somebody else's ) proprietary software. They are evil but they aren't that dumb

https://github.com/google/skywater-pdk

The SKY130 is a mature 180nm-130nm hybrid technology originally developed internally by Cypress Semiconductor before being spun out into SkyWater Technology and made accessible to general industry. SkyWater and Google’s collaboration is now making this technology accessible to everyone!


The SKY130 Process node technology stack consists of;

    Support for internal 1.8V with 5.0V I/Os (operable at 2.5V)
    1 level of local interconnect
    5 levels of metal
    Is inductor-capable
    Has high sheet rho poly resistor
    Optional MiM capacitors
    Includes SONOS shrunken cell
    Supports 10V regulated supply
    HV extended-drain NMOS and PMOS

You probably aren't building an LTZ1000 on that

[Fred Basset]

That's 35mm^2, which is pretty big for an IC. Many MCUs are smaller than that, as evidenced by the size of the packages they come in.
[/quote]

Could make a pretty good sensor chip though - If anyone has any ideas?

Whatever happened to Microsoft doing something similar for 3D tools?  We got paint 3D and that is all isn't it?  It was supposed to make 3D printers practically plug and play on W10.