General > General Technical Chat
Review: Hantek DDS 3X25. Anyone own one?
Mechatrommer:
--- Quote from: marmad on July 23, 2011, 01:39:19 pm ---True. If I can just get it to output a stable sweep sequence, I will be fine with everything else. And it may end up working - I'm trying a few tricks today.
--- End quote ---
as long as sweeping function is concerned, its workable, unless during the transition, you just have to wait a little bit before analyzing your circuit behaviour. you get what you pay, you've been warned by me (previous post) about the sweep function long before you buy this stuff. are you sure the velleman is truly stable on sweep? you may end up having unperfect sweep with slower frequency signal :P who knows. to get a perfect sweep i think you need to pay multiples of 3x25 price. maybe our next mission (hack) is to rewrite the fpga! and usb communication :P
marmad:
--- Quote --- DDS only convert digital data into analog data (wave) what else does it do?
--- End quote ---
No, no... Mecha - you're wrong. You're just talking about digital to analog conversion. DDS is more specific - there aren't multiple definitions - and there are certainly parts of the process missing from the Hantek, such as:
1) No lookup table -- every true DDS device I've seen has this as a base - minimum: sine, square, and triangle at full sample length stored in the device. No need to download data except for AWs.
2) No phase register and accumulator of 2^44 minimum -- think of this kind of like the clock divider plus the bits of vertical resolution -- this is the most important part, since true DDS yields precision in at least the 0.01% realm - not 0.1% like the 3X25 - which is a factor of 10 worse - and accounts for the "non-stable" frequencies. The 3X25 has a clock divider of approx. 2^16 plus 2^12 bits of vertical resolution.
True DDS works like this in software: Tell device what waveform you want (e.g. triangle) and the amplitude, offset, and frequency to 6 digits of resolution (e.g. 1.2378Hz) - it does the rest. Or download AW at full sample depth (e.g. 4096) and tell the device the amplitude, offset, and frequency - it does the rest.
--- Quote --- you've been warned by me (previous post) about the sweep function long before you buy this stuff.
--- End quote ---
Ha - one always likes to believe one can find solutions where others have not ;)
--- Quote ---you sure the velleman is truly stable on sweep?
--- End quote ---
Oh yes, well documented. But I will continue to see what I can do with this device before seriously thinking about jumping ship.
So, in that realm - attached are some PNGs of the digital outs of the Hantek clocked by the DAC.
1) The setup
2) 1MHz sine wave output - 3.5V pp - 0V offset -- notice sine wave of combined Generator outputs - and Gen11 as nice sync signal. Also notice all the activity on the bottom 4 pins of the Multiprocessor link.
2) 1MHz sine wave output - 1.75V pp - 1.75V offset -- now there are glitches occurring in the Generator outputs - I have no idea yet why that is happening with a voltage offset.
Edit: Just shrinking the images a bit for BW considerations
Mechatrommer:
--- Quote from: marmad on July 23, 2011, 02:40:09 pm ---Ha - one always likes to believe one can find solutions where others have not ;)
--- End quote ---
i know how that feels like ;) i hope you will
nice picture on your logic probing. strange i havent seen the glitch on 1.75V offset there, does it tally with digital data? ie can you see glitch in digital data as well?
you are tapping the dac pin? what is it clock? have you figure out what dac it is?
marmad:
--- Quote ---strange i havent seen the glitch on 1.75V offset there, does it tally with digital data?
--- End quote ---
Actually, I'm seeing other glitches now even without the offset - I'm starting to believe it's caused by the unbuffered, unpulled pins of the FPGA - but I will investigate further. It might be crosstalk.
--- Quote ---you are tapping the dac pin? what is it clock? have you figure out what dac it is?
--- End quote ---
Yep, pin 28 is the clock. I think it is the DAC you discovered earlier (ISL5857 or ISL5861).
marmad:
I've been trying to work out how the hardware clock divider works on the Hantek...
It seems any frequency > 48,828Hz, which is the maximum frequency the hardware could clock the full sample buffer (i.e. clock / sample buffer = 200MHz / 4096 = 48,828Hz) follows the formula:
clock / (sample length / sample step) = fOUT
where
sample length is an integer >= 2000 && <= 4095 [12 bits - it rolls to 4096 at 25MHz or above]
and
sample step is an integer >=1 && <= 2047 [11 bits]
You can easily determine the frequencies the device can handle - for example:
200MHz / (2000 / 1) = 100,000Hz
The next highest frequency the device can do is:
200MHz / (3999 / 2) = 100,025Hz
then
200MHz / (3998 / 2) = 100,050Hz
and so on. You can test this easily by feeding the output back into the frequency counter and trying to set the device to 100,010Hz in the Hantek software - it will instead go to ~100,025Hz.
The sample length and sample step numbers are what you get back when using the DDSSetFrequency command. But I'm not sure how the divider works for <= 48,828Hz since the numbers returned in that case don't make sense in a formula. I think that the undocumented DivNum setting is a part of the divider chain that's missing (in terms of math) for lower frequencies. When you try to SetDivNum (undocumented - I'm not sure how to call it correctly so I just send it a Long variable), the clock gets very slow and the frequency drops very low. Then you need to use SetFrequency to get it dividing correctly again.
Any thoughts, Mecha?
Navigation
[0] Message Index
[#] Next page
[*] Previous page
Go to full version