Simplistic question about modern CPU power architecture.

[clickcell]

Ok so let's say a modern CPU has 1,000 pins, suddenly a dumb question popped into my head:

Does each pin use an equal share of the total power draw? Or are there special power pins? Or could you plot the power usage of each pin on a normal distribution?

Anybody know?

[clickcell]

The pins on these devices are, as Dave would say, not even half a bees dick in size. So where is the 100 watts getting in from? Must be roughly an even share? I would say they all use the same amount of power and the number of active pins determines how much power the chip is using. Does that sound right?

[wraper]

Power don't go over just one pin. if you take 100 bees dicks, that becomes quiet a lot  Of course there are special power pins, just a lot of them. Did't get your "equal share", are you supposing CPU gets powered over data pins  ?

[clickcell]

And if each pin takes a tiny amount of power, what is the use of the 8 or so big voltage regulators next to the chip? How can you use 8 regulators to power 1,000 pins?

[clickcell]

Of course there are special power pins, just a lot of them. Did't get your "equal share" are you supposing CPU gets powered over data pins  ?

Yeah, I guess I'm pretty ignorant on this subject! I don't understand what's happening on the chip that allows the power pins and all the other pins to work. Seems like an interesting topic. Maybe for a video (lol, wink).

[wraper]

And if each pin takes a tiny amount of power, what is the use of the 8 or so big voltage regulators next to the chip? How can you use 8 regulators to power 1,000 pins?

They are not voltage regulators but MOSFETs. All they are used in multi phase step-down converter for Vcore.

[wraper]

How can you use 8 regulators to power 1,000 pins?
Heard of connecting the pins in parallel?

[clickcell]

Are the power pins spread out all over or on the sides or what? When I look at a die map there's no area that says "power management" or anything like that:

[sacherjj]

If you are talking about complex processors, there are often 6-12 voltage buses.  This means that the power for those subsections come from those pins.  We have a design with an Atom processor and I think we have 10 voltage buses, many are at 1.5V but for various sub systems on the processor.

The problem that chip makers are FINALLY solving is the location of power and ground right next to each other.  For the longest time, there was a group of pins, balls, pads that were VCC and a group that were VSS and a decent gap in between them.  This made decoupling a nightmare and loop currents a big problem.  Current flows in fields and the fields had to spread out far to big to get the job done.  This meant more EMI and more noise everywhere in the circuit.

So to try to answer your question, the current is pretty much shared over the pins on the same bus.  Looking at an i7 data sheet, while the voltage is only 1.5V, the max current is 145A!   

So we have the problem of just getting the power in there without melting everything.  And also getting the power in there without dropping a ton of voltage via resistance.  We also have to have a low inductance path, or we will starve the processor when it has a rapid power request.  All of these can be achieved with parallel feeds.  The inductance of the power path of a single ball or pin is pretty high.  But when you have 100 in parallel, it is a tiny fraction.  Just like the effect of sinking multiple vias to make their overall inductance lower.  At the response times we are now working with, even the power inductance going to the silicon becomes a factor.  100 little connections actually perform better than one big one.

[BravoV]

Are the power pins spread out all over or on the sides or what? When I look at a die map there's no area that says "power management" or anything like that:

Just download the cpu datasheet and look at the pins arrangement, how hard is that ? 

[sacherjj]

Are the power pins spread out all over or on the sides or what? When I look at a die map there's no area that says "power management" or anything like that:

Have you seen bonding of a silicon chip to a package?  There are gold bond wires that link the silicon to the package that you see to solder down.  Every sub section on there requires power.  All have power connections.

[Mechanical Menace]

Yes the more outputs that are driven high the more power they would use but it would be more than possible to fit something into cache that would use orders of magnitude more power than driving all possible output pins high. Multiplying two numbers together is generally about 4 times more energy expensive than addition for example. Working out powers could be 100 times more expensive than addition. Setting each core in a loop working out powers would be much more expensive than driving every output high.

Are the power pins spread out all over or on the sides or what? When I look at a die map there's no area that says "power management" or anything like that:

CPUs may have power management features but it's up to the OS (or other bare bones code) to actually tell them what to do. Changing the clock speed or powering down cores (where possible) would be done by the "uncore" section of the die but under the control of at least one of the CPU cores.

[clickcell]

The data sheet is nice but this thread is more interesting for the layman.

I've enjoyed the responses so far.

[daqq]

And if each pin takes a tiny amount of power, what is the use of the 8 or so big voltage regulators next to the chip? How can you use 8 regulators to power 1,000 pins?

In this case you have two types of pins - power and data. Power pins supply the power to the processor/device. On complex devices you can easily have a hundred or more pins dedicated to, say, +1.05V, another hundred (or more, GND is special) dedicated to GND (0V). When you connect these in parallel you get more current carrying capacity. One single pin can transport say, 0.5Amps without any problems. More than that pin resistance comes into play and you begin to lose voltage and gain heat - which at such low voltages and high currents is a problem. But you need to feed your processor, say, 70 Amps. So, you take 140 of these 0.5 Amp pins, use them in parallel and you're done.

As to the "8 regulators" - well, there are different kinds of requirements for different kinds of processors/devices. First off, you can essentially divide the load amongst several DC/DC converters (look them up), in which case you get a multiphase DC DC converter. Then you have different voltages - one part of the processor requires, say, +1.2V, the other one say +0.9V - you have to do this with a separate voltage regulator.

If you wish to see a really nasty schematic, check out:

http://cache.freescale.com/files/microcontrollers/hardware_tools/schematics/T4240RDBSCH.pdf?fasp=1&WT_TYPE=Schematics&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Downloads&fileExt=.pdf

At a quick glance there are  10 different voltages (page 4). See page 24 (and others) for examples on how many GND pins are used.

[NiHaoMike]

Things get really interesting with Haswell. In order to get around the high current through the pogo pins and associated losses (and to add finer "granularity" with more rails), they put a bunch of buck regulators on the CPU itself.

[jwm_]

Things get really interesting with Haswell. In order to get around the high current through the pogo pins and associated losses (and to add finer "granularity" with more rails), they put a bunch of buck regulators on the CPU itself.

How do they do inductors on the die? Or are they capacitive converters? I don't think the usual solution for an on die inductor, the gyrator, works for a DC-DC converter.

[daqq]

How do they do inductors on the die? Or are they capacitive converters? I don't think the usual solution for an on die inductor, the gyrator, works for a DC-DC converter.

Inductors:

http://www.hotchips.org/wp-content/uploads/hc_archives/hc23/HC23.17.1-tutorial1/HC23.17.121,Inductence-Gardner-Intel-DG%20081711-correct.pdf
http://www.psma.com/sites/default/files/uploads/tech-forums-nanotechnology/resources/400a-fully-integrated-silicon-voltage-regulator.pdf

It's pretty magical really.

[tom66]

The Intel solution used 30~100MHz DC-DC stage. Once you have no concerns about PCB layout, I guess you can use silly frequencies. Intel did ditch the design for Haswell Refresh though. Maybe it was too expensive to implement and we'll see it again in a few years when they figure out how to make it cheaper.

I'm guessing Haswell DC-DC did take a lower input voltage in still, but the regulation and exact range was not as critical? 12V in would require much larger MOSFETs.

[Jeroen3]

Here you go, a random pinout of a cpu. And the amps are also weird, easily 100 A. But at a low voltage, so there is less power.

[amyk]

This is what happens when the contact resistance gets too high on some pins:

http://www.anandtech.com/show/2859

[Jeroen3]

Thats why the shop, the manuals and every smart guy tells you to NEVER TOUCH THE GOLD CONTACTS.