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The End of Electrical Engineering Design?
MT:
In a solar system not far from you a planet filled with scientific fraudsters:
Google placed senior software engineer Blake Lemoine on leave after he went public with his belief that the company's artificial intelligence (AI) chatbot LaMDA was a self-aware person.
https://www.washingtonpost.com/technology/2022/06/11/google-ai-lamda-blake-lemoine/
https://www.reuters.com/technology/its-alive-how-belief-ai-sentience-is-becoming-problem-2022-06-30/
Its alive, its alive, now i now how it feels to be a scientific lunatic! Criticizing Me Is Criticizing Science ;- Dr Fausti.
--- Quote from: free_electron on July 12, 2022, 04:47:36 pm ---meh... another fad based on clown (cloud) computing.
This nothing more than assembling kits based off demoboards. This is NOT board design. as for intelligence ? most 8 year olds can do better
Watch this as they show absolute crap schematics built using their 'blocks' (featherwing here, other hobby crap there) and then 'route'
(it's more like somebody regurgitating a plate of squid pasta and then throwing a firecracker in it and take a picture of what stuck to the wall)
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That Karim Beguir is deep in with vaccine maker BioNTech and German railway Deutsche Bahn etc, so what could possibly go wrong.
thm_w:
--- Quote from: coppice on July 13, 2022, 01:19:10 pm ---
--- Quote from: free_electron on July 12, 2022, 06:39:18 pm ---
--- Quote from: Benta on July 12, 2022, 05:43:36 pm ---Idiotic spin.
PCB design today is 5% of design effort and has very little to do with engineering. It's more in the Draftsman trade.
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You've probably never seen a real pcb.
Try a modern motherboard. or a high power inverter with embedded transformers. Maybe something with all kinds of controlled impedance, signal integrity, looptime compensation , 8 layers, embeddded heat medallions, embedded wires , stacked / dogboned laservias / vippo / elic ? something that has 0.5mm BGA's and 1000 ampere running through it and 800 volts busbars. Then you will understand how much engineering goes in the board. Without that engineering your nice schematic is SNOT. if the layout is not done properly , at switch-on time you'll end up with a smoldering crater where once was your lab bench.
The time where draftsmen made single layer hand taped stuff for through hole parts is over.
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So, why are only 5% of the engineers doing PCB layout in a typical design centre?
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The statement was PCB design is 5% design effort.
The number of engineers doing PCB layout is completely unrelated to that number.
If we were talking about TOTAL design hours or effort for a project, then there would be some relevance.
coppice:
--- Quote from: thm_w on July 13, 2022, 07:59:05 pm ---The statement was PCB design is 5% design effort.
The number of engineers doing PCB layout is completely unrelated to that number.
If we were talking about TOTAL design hours or effort for a project, then there would be some relevance.
--- End quote ---
So, you are claiming that 5% of the effort is not 5% of the man hours? You've lost me.
nigelwright7557:
I wrote my own pcb design software.
I found a good way to minimise size was using a "swap autoplacer" which swaps 2 components at a time if doing so shortens net.
Its a little smart in that you can make components none movable if you want.
It result in about 2-5% better autoroute results.
Auto pcb design:
To route a pcb some parts need to be in fixed positions so the operator would need to set these.
Some pcb's require star grounding on some nets so these would need to be high lighted.
On audio pcb's mains and mains transformers need to be away from high impedance audio.
On audio some paths need to be minimal length so these would need to be highlighted.
A good pcbcad man shouldnt be underestimated.
ConKbot:
Freebie for the startups that are actually interested in doing more than collecting investor cash. ML driven PDN optimizing. Would be something applicable to ML, actually useful, and not a pie in the sky wankfest. X ASIC pins are defined as power, need <y milliohm upto n GHz impedance for them, and z transient response. Let it pick though a library of caps with parasitics modeled, then place and stitch them to power planes, and then optimize for lowest space, lowest cost, flattest response across all the pins, or whatever other metric.
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