General > General Technical Chat
The End of Electrical Engineering Design?
<< < (7/8) > >>
free_electron:

--- Quote from: ConKbot on July 14, 2022, 08:15:36 am ---Freebie for the startups that are actually interested in doing more than collecting investor cash. ML driven PDN optimizing. Would be something applicable to ML, actually useful, and not a pie in the sky wankfest. X ASIC pins are defined as power, need <y milliohm upto n GHz impedance for them, and z transient response. Let it pick though a library of caps with parasitics modeled, then place and stitch them to power planes, and then optimize for lowest space, lowest cost, flattest response across all the pins, or whatever other metric.

--- End quote ---
that could be interesting. especially resonance points. the problem is the capacitor data. every manufacturer has a different approach.
Murata and others already has free tools to do this. but you need to pick manually. if that could be automated. then again ... not sure you need an AI , can be done with simple loops. the computer speed we have now could try all combinations in a few seconds.
Someone:

--- Quote from: free_electron on July 14, 2022, 01:52:10 pm ---
--- Quote from: ConKbot on July 14, 2022, 08:15:36 am --- ML driven PDN optimizing. Would be something applicable to ML, actually useful, and not a pie in the sky wankfest. X ASIC pins are defined as power, need <y milliohm upto n GHz impedance for them, and z transient response. Let it pick though a library of caps with parasitics modeled, then place and stitch them to power planes, and then optimize for lowest space, lowest cost, flattest response across all the pins, or whatever other metric.

--- End quote ---
... not sure you need an AI , can be done with simple loops. the computer speed we have now could try all combinations in a few seconds.

--- End quote ---
lol, you talk big about how PCB design is complex and uses field solvers so it’s not just heuristics and untangling….  but forget? PDN design/tuning is intimately tied to layout and PCB routing + stackup.

So we’ll take you down a peg and remind you that Engineers (your choice of distinction) do the work, and PCB is mostly accumulation of grunt work with little engineering when viewed even from your perspective.

Lots of PCB design time is a human doing untangling, shifting things around so it all fits. Computers will keep taking more of that work.

I’ll get back to damping planes by moving parts and shuffling copper to balance IR drops since the “PCB drafters” are a) not able to recognise the issues, and b) don’t have visibility on the requirements.

That last point is the bottleneck/impedance mismatch with designing PCBs. Many many many competing criteria, and trying to communicate the full set of requirements. When for most decisions in layout 99.9% of the list of requirements don’t apply, and on a multi person layout most of the workers won’t even need to know most of the requirements.

App notes or reference designs often err on the side of caution/conservative design so it can be blindly reused without thinking required. Dig a little deeper and all of a sudden half the decoupling capacitance disappears, and all those keep-out/unbroken-plane directives can be filled with (non aggressor) curcuitry. Time vs money, but some things can carry the investment. That is not buying more PCB layout/drafting but better input/instruction for them.
thm_w:

--- Quote from: coppice on July 14, 2022, 02:11:43 am ---
--- Quote from: thm_w on July 13, 2022, 07:59:05 pm ---The statement was PCB design is 5% design effort.
The number of engineers doing PCB layout is completely unrelated to that number.

If we were talking about TOTAL design hours or effort for a project, then there would be some relevance.

--- End quote ---
So, you are claiming that 5% of the effort is not 5% of the man hours? You've lost me.

--- End quote ---

Yeah you are right I clearly misread.
If we are talking about total project effort, including software, I can see around 5% generally. Although that doesn't mean the work is any easier or harder, its just a portion of the task.
free_electron:

--- Quote from: Someone on July 14, 2022, 02:58:56 pm ---
--- Quote from: free_electron on July 14, 2022, 01:52:10 pm ---
--- Quote from: ConKbot on July 14, 2022, 08:15:36 am --- ML driven PDN optimizing. Would be something applicable to ML, actually useful, and not a pie in the sky wankfest. X ASIC pins are defined as power, need <y milliohm upto n GHz impedance for them, and z transient response. Let it pick though a library of caps with parasitics modeled, then place and stitch them to power planes, and then optimize for lowest space, lowest cost, flattest response across all the pins, or whatever other metric.

--- End quote ---
... not sure you need an AI , can be done with simple loops. the computer speed we have now could try all combinations in a few seconds.

--- End quote ---
lol, you talk big about how PCB design is complex and uses field solvers so it’s not just heuristics and untangling….  but forget? PDN design/tuning is intimately tied to layout and PCB routing + stackup.

So we’ll take you down a peg and remind you that Engineers (your choice of distinction) do the work, and PCB is mostly accumulation of grunt work with little engineering when viewed even from your perspective.

Lots of PCB design time is a human doing untangling, shifting things around so it all fits. Computers will keep taking more of that work.

I’ll get back to damping planes by moving parts and shuffling copper to balance IR drops since the “PCB drafters” are a) not able to recognise the issues, and b) don’t have visibility on the requirements.

That last point is the bottleneck/impedance mismatch with designing PCBs. Many many many competing criteria, and trying to communicate the full set of requirements. When for most decisions in layout 99.9% of the list of requirements don’t apply, and on a multi person layout most of the workers won’t even need to know most of the requirements.

App notes or reference designs often err on the side of caution/conservative design so it can be blindly reused without thinking required. Dig a little deeper and all of a sudden half the decoupling capacitance disappears, and all those keep-out/unbroken-plane directives can be filled with (non aggressor) curcuitry. Time vs money, but some things can carry the investment. That is not buying more PCB layout/drafting but better input/instruction for them.

--- End quote ---
i'm talking finding the best combination of caps . once you know what and how much , the combinations can be looped very quickly. PDN analysis software has existed for a long time. no AI needed. You do a proper placement (so the board is not swiss cheese), see where you land , and then go tune the caps (if needed). The models now are good enough. 20 years ago you had to sit in the lab with a network analyser . Now the capacitor makers have accurate models.
Any serious board designer does that. The time of menial line drawing is over. You work with the people responsible for the design to tune those things.
Someone:

--- Quote from: free_electron on July 14, 2022, 01:52:10 pm ---The models now are good enough. 20 years ago you had to sit in the lab with a network analyser . Now the capacitor makers have accurate models. Any serious board designer does that.
--- End quote ---
Yes, the models are now more accurate than ever and simulation can get accurate enough to dispense with the network analyser in most cases. Do I see PCB teams doing that work? Never have, that was left for separate PDN specialist(s) who weren't doing PCB layout as their day-to-day tasks. Very few individuals end up at that level of detail.


--- Quote from: free_electron on July 14, 2022, 09:27:27 pm ---
--- Quote from: Someone on July 14, 2022, 02:58:56 pm ---
--- Quote from: free_electron on July 14, 2022, 01:52:10 pm ---
--- Quote from: ConKbot on July 14, 2022, 08:15:36 am --- ML driven PDN optimizing. Would be something applicable to ML, actually useful, and not a pie in the sky wankfest. X ASIC pins are defined as power, need <y milliohm upto n GHz impedance for them, and z transient response. Let it pick though a library of caps with parasitics modeled, then place and stitch them to power planes, and then optimize for lowest space, lowest cost, flattest response across all the pins, or whatever other metric.
--- End quote ---
... not sure you need an AI , can be done with simple loops. the computer speed we have now could try all combinations in a few seconds.

--- End quote ---
lol, you talk big about how PCB design is complex and uses field solvers so it’s not just heuristics and untangling….  but forget? PDN design/tuning is intimately tied to layout and PCB routing + stackup.
--- End quote ---
i'm talking finding the best combination of caps . once you know what and how much , the combinations can be looped very quickly. PDN analysis software has existed for a long time. no AI needed. You do a proper placement (so the board is not swiss cheese), see where you land , and then go tune the caps (if needed).
--- End quote ---
Unless you disregard the plane (then why use a field solver you proudly pointed to in your box of tools?) the minimum combination/sizes of capacitors changes with their layout/positioning on the plane(s), they can be optimized for a given layout rather than a pessimistic solution that works for any reasonable plane/layout. Shifting a few caps 10mm or so around can make big differences, and it's those incremental optimisations that are amenable to automation.

Take a "typical" SoC/FPGA/ASIC rail with 40-50 capacitors on it, and a selection of a dozen or so caps stocked (and always loaded on the pick and place), that's 50^12 >= 200e18 combinations, not a problem that can be solved "quickly" by brute force.

You're talking big but the few of us who actually know this stuff see right through the bluster, or perhaps continue and embarrass yourself further?
Navigation
Message Index
Next page
Previous page
There was an error while thanking
Thanking...

Go to full version
Powered by SMFPacks Advanced Attachments Uploader Mod