General > General Technical Chat
The Rigol DS1052E
dealexcel:
Ted come here again, if you guys are still interested in ds1052e scope, welcome to my site anytime 8)
Mechatrommer:
--- Quote from: dealexcel on November 02, 2010, 03:53:48 am ---Ted come here again, if you guys are still interested in ds1052e scope, welcome to my site anytime 8)
--- End quote ---
update your own thread! >:( :P
EECrAZY:
Turns out that I was right in my previous post, single DAC output is multiplexed and used to generate multiple voltages for A,B offset as well as trigger level.
Interesting thing is that it also generates a saw like voltage with 2seconds period! Any ideas what it can be used for? I was not able to trace where its output goes.
Another interesting thing is they always clock ADCs at 100MHz, even at the lowest sampling rate. So I guess FPGA just skips unwanted samples. Would be nice if it could go down to 20Mhz at lower sample frequencies, I am sure it would reduce the heat quite a bit
EECrAZY:
Rigol’s 1Gs interleaved ADCs seem to be a problem and completely useless at higher frequencies
Upon further analysis of their schematic, it turns out that all ADCs are clocked directly from Cyclon III FPGA. Looking at the datasheet, Cyclon III PLL has 300ps of jitter on the output clock… that means sample uncertainty of 300ps! Using a standard equation we can determine that at 100Mhz input frequency, we have SNR of only 20db! Or effective resolution of 3.4 bits.
Note that unlike offset and gain errors, those 300ps are random and can not be corrected by any digital post filtering
Please correct me if I missed something. Any ideas from the experts?
Fraser:
Hmmmm. 300ps jitter present at all times or maximum of 300ps jitter worst case scenario. There is a difference.
We already know that Rigol have employed some clever(?) tricks to provide a 1Gs/s DSO at a great price. Should we not be testing and reporting the real world performanace rather than using a chip manufacturers worst case scenario jitter figure ? Just a thought.
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