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| The Rigol DS1052E |
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| EECrAZY:
yeah, 300ps is a 10^-12 probability (14 sigma) peak to peak jitter. So really it translate to 20ps rms jitter which would give us 44 db SNR or resolution of 7.3 effective bits. I agree that this tool is worth the money, One thing I dont like, they pushed it to 1Gsa for marketing purpose because higher numbers bring customers. They know most of us cant really tests the performance up to the limits, especially considering a low end market. I would really like to see some real life measurement at 100+ Mhz input and 1GSa. I bet you should be able to see some noise due to interleaving multiple ADCs |
| tinhead:
correct me if i'm wrong, but isn't for interleaved ADCs the clock shit accuracy more important ? That's 50ps between rising edges of each clock period (which is probably measure period). In a worst case we can still solder 10bit ADCs (AD9218, pin compatible to AD9288) and use only 8 MSB bits ^^ |
| EECrAZY:
--- Quote from: tinman on November 06, 2010, 09:16:57 pm ---correct me if i'm wrong, but isn't for interleaved ADCs the clock shit more important ? That's 50ps between rising edges of each clock period (which is probably measure period). In a worst case we can still solder 10bit ADCs (AD9218, pin compatible to AD9288) and use only 8 MSB bits ^^ --- End quote --- In ideal world you would have 10ADCs sampled at 10ns with 1ns phase shift. Lets say due to clock jitter this phase shift varies randomply from 0.9 to 1.1 ns. That creates an uncertainty window of when sample is digitized. Using a 10 bit ADC makes no difference if effective number of bits is 7. You only need 7 bits to resolve your signal above the noise floor. 3 LSBs will be randomly floating (measuring random noise). In case of 8 bit ADC 1 bit will be measuring noise 50 ps phase shift error you mentioned is constant. Unlike random jitter, it can be eliminated by calibration. |
| tinhead:
Exact, in the theory each ADC is sampled with 1ns phase shift with no jitter. The sampled data is available always on rising edge (actually after aperture delay). The 300ps PLL jitter is a full period jitter, but we still within one period so the "jitter" is only ±50ps due PLL shift inaccuracy. After such full sample cycle of course there can be 300ps jitter to next rising edge but that's different story, there will be anyway "a window" due 2000 waveforms/sec. Not sure how Rigol is using the ADCs, but probably with data align enabled - each ADC in AD9288 shifted by 180° and all AD9288 shifted by 2ns to each other. btw, the 10bit ADC was a joke ^^, it will requiere clock with less jitter anyway. |
| EECrAZY:
Well, yes and no. May be data within 1 period is indeed not affected by period jitter. But you still need to have evenly spaced samples. Looking at 10ns of data is impractical in most cases, so you will see visual distortions and much more noise on FFT. Actually, I dont believe AD9288 data align provides 180 degree phase shift. Its only for the output, data is still sampled independently on the rising edge of each clock. But output from channel B is 1/2 period delayed. |
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