Newly minted engineer (NM), straight out of uni. Masters. Analog design.
Walks into my lab with 'underwhelming enthusiasm' because he is tasked with debugging an actual board as opposed to simulating it at his desk.
NM walks to large cabinet with parts , opens and closes drawers , get's a more and more puzzled look on his face and lumbers over to me.
NM: how can i tell for these small components (smd) what are resistors and caps. They all look the same...
ME: look at the label on the bins. The capacitors have their a little omega symbol behind the value.
NM: ok
NM rifles through cabinet and walks off with his 100kilo-pico decoupling cap.....
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PE ( paper engineer . Type that only shuffles paper around but has no practical experience. Never leaves desk ) comes to lab , has to do something on. Aboard. He is given a prototype chip and has to test power consumption on the 1.8 volt rail.
He messes around for a while and cant get it to work . Calls for help.
I walk over there .. One huge ball of wires going everywhere.. I trace all the wires out. His ammeter wires , through lots of bananas and grabbers were both connected to the 1.8 v rail... So in essence the ammeter is shorted and connected to 1.8 volt.
I explain to him current needs to flow through the ammeter. I also explain that , in order to do that there is a nice jumper on the board that disconnects the 1.8 volt plane feeding the chip , from the regulator.
PE mucks about for another half hour and calls me over. He has blown the fuses in 3 ammeters.. I look at the wiring. The ammeter is now connected from the 1v8 regulator out to .... Ground... It is supposed to be between the pins of the jumper. It aint a voltmeter ! Anyway , we were out of fuses ( and working ammeters) so i tell him : take a bench supply , set it to 1.8 volts , connect to jumper and read the current from the supply. I walk off.
A few moments later i become awar of that typical smell of carbonised ic packages... Following my nose leads me to PE's bench....
Sure enough. The nitwit now connected the supply between the jumper pins. So he had 1.8 being made on the board , in series with 1.8 made by the supply , thereby feeding 3.6 volts into the chip...
He looks at me and say : there must be something wrong with these prototypes they all blow up at poweron...
ME : how many protos do you have ?
PE : 5
ME : how many did you try
PE : 5
ME : i guess it must be a production problem then. Its very consistent . They all blow at 3.6 volts...
PE happy trundles off to write report... Not catching on to what i just said. Sure enough during slide presentation he made a nice bullet point : all chips blow at 3.6 volts.. As this is consistent it must be a fab problem....
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PE2 ( a different one) is tasked to design some glue logic to match a pcmcia wifi network card( pcmcia is basically isa) onto the memory interface of a chip. We want to add wifi capabilities and use simple pcmcia cards for that purpose (2001 era. Every router was built that way then)
He comes up with a circuit consisting of 11 or 12 ttl chips (74xx series). Most of em half used. Like a 7404 because he needs an inverter somewhere.... And there is an u used 7400 gate left...
I go over the schematic and manage to reduce the circuitry to 5 chips.( he used 74245 as bus switch on data . I happen to know there is such thing as a 16245 for 16 bit buses.... ) no comment on that , i just happened to know that, he didn't. That was not the problem.
I had minimized his pile of loose gates to two quad nand, a quad nor and a quad and. Or something like that. I had built an or gate from three nands. Simply make two inverters out of two nand gates, and slap on another nand gate.. A+B = not(notA * notB) . Simple boolean logic.
He doublechecked my circuit ( as he was responsible for signoff) andexclaimed this could not work. He definitely needed an or gate for the two signals and i must have made a mistake. I tried explaining him boolean rules.. But no budging on his side. Anyway, he was going to make a quick netlist in VHDL based on my schematic and send it through the simulator....
This made me print a large banner to put over his desk.. The banner said 'More TTL, Less VHDL'
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Chinese collegue with -very- bad pronunciation...
RING.. ( telephone). We need talk abou alice. Alice no good.
? This guy has a complaint about alice ? I look around puzzled .. I don't know any alice in the department ( i had just started there like a few weeks before ) . So i ask my collegue if they know any alice .. Puzzled looks . No, we don't have anyone in the company with that name.
I turn back to the phone and ask if he is sure he got the right guys ?
Him : Yes yes alice wok fo poi fai.
? What the hell ? Alice.. And she works for some asian sounding guy called 'poifai' .. So i turn to my collegue and say that this dude wants to talk to 'alice' who works for some guy called something that sounds like poifai.
At this point the senior designer starts laughing and asks who i am talking to ... I give the name. .. He says , okay i know what this is about pass him to me. So we all look baffled .. And he explains :
This chinese guy has been working on the 'Netlist' for the first chip in 0.5 micrometer technology (this was 1993...)
So he found a problem in the 'netlist work for point five...'
Alice wok fo poi fai...
....
The same chinese dude drew massive crowds whenever he gave a presentation. People went there for laughs ... One meeting he was explaining a block he designed and he kept going on about some jibberish.. Lingoselelle or something like that. The senior designers were all baffled. We were used to chinglish by now but this was a rightout brainracker... Until 5 minutes later one of the seniors , who had been diggi g in the schematics exclaimed: i know what this is. It's the ringoscillator he used here:
Yes yes, lingoscelelle..
Other instances : the atela... ( talking about the altera fpga on the board )