The noise is answer to this question. 24 or 32-bits ADC should be weighted vs data rate, all of ADC I know have less than 16 noise-free bits above 1 ksps. In other words, last one or two bytes just garbage -not data.
Recently I was digging into 4 channels ultra low noise aquisition sustem, and didn't find any "ready" solution, have to build my own.
There are some good DS (SD) adc from AD, ad7124, ad7172, some from Cirrus Logic CS5534 - low noise ONLY with low data rate, < 30 sps. More over, all of the single channel - multiplexed.
Using high speed 1 msps SAR is not an option, again single channels only, and if try to do multipliplexing - forget about 1 nV. Seems like conspiricy, switches - bugged, there are no "slew rate switching control" on a market. AZ amplifier - bugged as well, no way to get access to internal switching frequency to have ability synchronize sampling - do glitch reduction.
So, to get 1 nV noise I have to solder amplifier.