SOA of FET in linear region

[Ice-Tea]

So.. I'm part of a design where a FET is used as an inrush current protection. Works nicely, but I'm having trouble guaging whether the FET operates within it's SOA. The waveforms are too irregular to make any kind of approximation.

The waveform and datasheet are just an example, but how would you go about this? How would you give a go/no-go?

Before you say: just pick a bigger FET, that's not an option. This is the kind of project where you'd get a pad on the back if after two weeks searching you'd shave off a 0.01$

[nctnico]

Multiply voltage by current to get power. Look at the current & voltage at the maximum power and use the width of the power pulse as the duration. A SOA graph basically is peak power during a given time but I see the datasheet you have also shows peak power for a certain duration. I strongly suggest derating enough so you have at least 50% margin in the worst case scenario.

[2N3055]

Exactly what Nctnico said.  It's a peak power that is important here. You can make a plot in LT spice, V(n002)*I(V1). It will show you power pulse..
But by just looking at it, I can see the point where you have 12V*5A=60W .. that is too much for that transistor as seen in Fig.10 of the datasheet.
So you need transistor that can at least have 60W/ 1-2 msec rating, and then, as Nctnico well said, you might want to derate it 30-50% to be sure.. If you need super reliable, derate 100%.

Regards.

[Ice-Tea]

Well, I was already plotting power (need to have input - output voltage for that, not output voltage as in the first plot). But then you're exagerating quite a bit, no? Then you're saying that you have that peak power during the entire pulse, which is far from the truth?

Totally agree on derating though.

[nctnico]

You have to use the voltage across the MOSFET and the current through it.

[Ice-Tea]

Which is used for the aquamarine power trace. But if you take peak power for the entire pulse... Seems a bit much. Was looking for something more accurate...

[Kleinstein]

If the shown SOA is true, the MOSFET is just power limited, with no thermal instability. In this case calculating the power at any time and using that as a load is ok. In principle there would be a way to even account for a more complicated shape when using the thermal impedance.

The big problem however is, that modern low voltage MOSFETs usually don't have a power limited FBSOA. So chances are that the shown SOA curve just reflects the thermal impedance curve and is ignoring possible thermal instability. So it might be worth getting a better data-sheet. At least have a look at one of a similar part from a manufacturer that usually includes full SOA curves. The new DS from Infineon are good examples.

[Ice-Tea]

I'll dig up some recent infinions as a reference.

In the meantime, I'm thinking average power over the pulse would not be a bad idea? Would be a decent indicator of energy dumped into the device. And then use the transient thermal impedance for the total pulse width. This would already be a derating on it's own. 

[nctnico]

Bad idea because you will likely exceed the SOA limits that way. I don't see the problem. Your event is 4ms which takes you already into a region of the SOA graph where massaging the numbers isn't going to gain much more room. I'd try and stay under to 10ms line and be done with it. If you want to save money you can try to find the cheapest MOSFET which satisfies the RDSon requirements and go from there. After all you don't need a very fast MOSFET or one with an extremely low gate charge.

[2N3055]

Well, I was already plotting power (need to have input - output voltage for that, not output voltage as in the first plot). But then you're exagerating quite a bit, no? Then you're saying that you have that peak power during the entire pulse, which is far from the truth?

Totally agree on derating though.

I'm sorry, I presumed you were plotting voltage over mosfet, and that's why 60W.. Which would be to much even for a 1ms pulse, not to mention 4-5 ms you have here...
With this curve, I would say it might be just enough to survive for some time, but with no reserve... I would not be comfortable.

Also Kleinstein well pointed out, datasheet doesn't show secondary slope on SAO connected with thermal runaway when operating in linear mode, that can be even more restrictive.
But in this case, since this is inrush limiter, treating it as a single pulse power limited would be probably ok... But as I said at the limit. I would like a bit reserve on top.

Regards.

[digsys]

Having designed many LDO FET regulators, and destroyed 100s FETs to create "real" SOA curves, I can assure you, MOST the data sheets provided
are NOT accurate, some woefully over-rated. There's already been a big thread on this, so it's an easy search.

[Ice-Tea]

If you want to save money you can try to find the cheapest MOSFET which satisfies the RDSon requirements and go from there.

Oh, this is not an 'or' story. This is an 'and' story: the one with the worst specs we can allow, from the least reputable brand in the smallest package. I'm still stunned on a daily basis how cheap these things are.

Thanks for all the input guys. I'll have to look into thermal runaway, even if it is not applicable right now. New to me, so very interesting indeed! I'll probably end up close to Ntcino's suggestion on how to determine allowable current shapes.

Thanks all!