Author Topic: Wafer scale chip  (Read 3940 times)

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Offline Red Squirrel

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Re: Wafer scale chip
« Reply #25 on: September 05, 2019, 06:06:23 pm »
I guess structural integrity could be an issue and might be why chips are kept physically small.  Say you stuck this thing on a PCB and the entire product is basically a giant COB, even slight flex in the board might crack the internal chip.   That, and thermal management might be an issue too.  I guess by sticking a huge heat sink on the entire chip you would kind of solve the heat and structural issues at same time though.  The heat sink could even be part of the manufacturing process and the chip ships with it.  Or at very least a thick metal plate where you put your own heat sink. 
 

Offline nimish

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Re: Wafer scale chip
« Reply #26 on: September 05, 2019, 07:03:04 pm »
This is the full hot chips presentation: https://secureservercdn.net/198.12.145.239/a7b.fcb.myftpupload.com/wp-content/uploads/2019/08/HC31_1.13_Cerebras.SeanLie.v02.pdf

Goes over all of the concerns. Power, cooling, fabrication, packaging.

 

Offline coppice

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Re: Wafer scale chip
« Reply #27 on: September 05, 2019, 07:16:52 pm »
This is the full hot chips presentation: https://secureservercdn.net/198.12.145.239/a7b.fcb.myftpupload.com/wp-content/uploads/2019/08/HC31_1.13_Cerebras.SeanLie.v02.pdf

Goes over all of the concerns. Power, cooling, fabrication, packaging.
It mentions the concerns. The answers are little more than hand waving.
 

Offline coppercone2

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Re: Wafer scale chip
« Reply #28 on: September 05, 2019, 09:56:19 pm »
do you know how much strain a heat sink bonded to a big ceramic block is?
 

Offline coppice

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Re: Wafer scale chip
« Reply #29 on: September 05, 2019, 10:28:28 pm »
do you know how much strain a heat sink bonded to a big ceramic block is?
From zero upwards. It depends how you mount it, and it depends how well arranged the thermal expansion rates are.
 

Offline SiliconWizard

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Re: Wafer scale chip
« Reply #30 on: September 05, 2019, 10:57:19 pm »
Take the "A" strain!
 

Offline matthurd

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Re: Wafer scale chip
« Reply #31 on: September 07, 2019, 12:54:57 pm »
Pretty stunning development. Hard to imagine 15kW for one wafer or 15MW for a wee cluster ;-)

They discuss the five challenges:
  1) redundant wafer routing that minimises latency - still a ns or two to cross the wafer though
  2) handling yield by routing around 1 to 1.5% of failed tiles
  3) thermal expansion - 15kW not evenly distributed generates a tad bit of uneven hotness and differing expansions => inventing new thermal materials
  4) packaging, “How on earth do you package it? Well, the answer is you invent a lot of shit. That is the truth. Nobody had a printed circuit board this size. Nobody had connectors. Nobody had a cold plate. Nobody had tools. Nobody had tools to align them. Nobody had tools to handle them. Nobody had any software to test,” Feldman explained.
  5) substrate design for power delivery (z-dimension) and cooling - liquid cooling with multiple zones and many ingress and egress water ports per wafer
 
Trilogy tried starting in 1980 by Gene Amdahl: https://www.nytimes.com/1984/08/10/business/trilogy-drops-wafer-scale-chip.html but he gave up saying it would take 100 years and pivoted to Elxsi and VAX clones but now does restaurants and sewer inspections equip (full life cycle?) plus some video processing stuff.

Crazy Clive Sinclair nearly pulled the rabbit out of the hat with Anamartic:  http://www.computinghistory.org.uk/det/3043/Anamartic-Wafer-Scale-160MB-Solid-State-Disk/

You wouldn't like to be Graphcore reading about this wafer-scale stuff. Makes your $300M IPU dev look anaemic.

It helped their founders, the main man Andrew Feldman, cashed out selling SeaMicro to AMD: https://www.gsb.stanford.edu/faculty-research/case-studies/cerebras-tale-dreams-risks
Three and a half years of dev seems a pretty quick result. Some product already being trialled by customers. Colour me impressed.

--Matt.

ref: https://techcrunch.com/2019/08/19/the-five-technical-challenges-cerebras-overcame-in-building-the-first-trillion-transistor-chip/
and https://www.forbes.com/sites/tiriasresearch/2019/08/20/ai-start-up-cerebras-develops-the-most-powerful-processor-in-the-world/#e94d86265924
 

Offline coppice

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Re: Wafer scale chip
« Reply #32 on: September 07, 2019, 01:01:45 pm »
Crazy Clive Sinclair nearly pulled the rabbit out of the hat with Anamartic:  http://www.computinghistory.org.uk/det/3043/Anamartic-Wafer-Scale-160MB-Solid-State-Disk/
I used to know the guy behind that technology. He was pushing the idea in the 70s, as a way to deal with the horrible low silicon yields of the time. It took until the end of the 80s before someone would actually fund a prototype. It worked as expected, but they couldn't get enough momentum to keep the work going.
 
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