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What must one revise for interview for senior FPGA design engineer position?
matrixofdynamism:
Different companies have different approaches. However, for those that have gone through the interview process enough times, they can certainly give their 2c. So my question is, what is the correct way to get prepared for a senior FPGA design engineer interview? What topics must one revise? Certainly knowing about adders and timing analysis is just the tip of the iceberge.
Someone:
If its a senior role, then you should already know!
tggzzz:
--- Quote from: Someone on January 31, 2022, 12:24:54 am ---If its a senior role, then you should already know!
--- End quote ---
Beat me to it!
Revising is not useful. The OP should be able to demonstrate that they have used all the relevant techniques.
Having said that, revising for the general interview process and numbskull HR-droid questions can be valuable. Whenever I was in that position, I found I messed up the first few interviews - so I chose jobs that I wasn't reallty interested in.
free_electron:
all you need to know is to always use the largest one with the fastest speed grade. you will exhaust its abilities no matter what.
all the rest is icing on the cake.
tom66:
You should probably know Verilog or VHDL :-) (which one is not really that vital, they are quite similar once you know one you can learn the other.)
If you don't know either of these, there's really no point in continuing...
If you do know HDL, then the chances are good you will know what types of questions will come up.
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