Who designs pinouts for processors and why do they hate customers?

[daqq]

Hi guys,

I'm just doing something with a STR912FAW46 processor and its networking. And I'm seriously getting stabby. The interface to the network IC is pretty much evenly distributed into two sides of the four sided IC (128 pin LQFP), with a pin or two actually being on ANOTHER side - one of which is the PHY_CLK signal, which is just jolly.

You might think, so what? It's a big interface. Oh no. The interface is a little less than 20 digital IO pins. On each side this is interlaced with pretty much anything that came to the sick bastard's mind to slap in there - JTAG? Sure, Digital GPIO? Yup, got it. Parallel memory interface? Check! A load of potentially useful IO with fun functions? Have those!

I'm OK with power pins coming out of all over the place, but seriously? Would it make baby Jesus cry to put the six bloody JTAG to six pins actually right next to each other instead of pins 89, 97, 111, 108, 107, 117 and 115? Or have the ethernet interface occupy the pins of ONE side? And they even could be next to each other. Instead, some are on 67, 71, 76, 78, 85, 88, 90... Oh, the TX part is fun - pins 99, 101, 106... But wait, isn't the BLOODY MAIN 25 MHz CRYSTAL SUPPOSED TO BE THERE?! Why yes, smack in the middle of the ethernet interface lies the main crystal on pins 103 and 104. Right around it is the JTAG interface as well.

I mean... seriously, what kind of bastard does this? Do they understand the concept of making your customer happy? Routing friendlyness perhaps? Did they actually LOOK at the stuff they made? Or just waved their hand "eh, they'll be fine"...

David

[amyk]

I'm guessing it has a lot to do with how the die is laid out. free_electron might know a bit more about why...

[cloudscapes]

I was wondering the exact same thing last week. 

I'm using SPI1 on a PIC32. SCK, SS and MOSI pins all next to each other on the chip, and MISO way the hell on the opposite side of the 100 TQFP. Thanks microchip! I didn't think my pcb layout had quite enough vias yet! How's 15 more!?!

[free_electron]

clocknets are typically injected in the middle of one side so they can be evenly distributed to prevent race conditions.

Now, for a number of processors the pinning does look stringe ... unless you consider that things like JTAG are typically wired to testpoints on the BACK of the board so they can be contacted by the board tester in-circuit...

I have seen chips that looked like they had completely wonky pinouts , until you mated them with the particular phy they were designed with. then it all lined up...

[marshallh]

It isn't designed to make you rage, usually its they way for a good reason, that you may not understand.
Look closely on the manufacturer's page for application notes, sample layouts, layout guides etc.
128 pins isn't that many, how many layers are you working with? If not 4layer already consider going to that.

[Stonent]

When I got my TI MSP430 Launchpad, it came with 2 chips, and one had about 4 more pins than the other but were identically pinned. Where you could basically stick the bigger one in the smaller socket with 4 pins hanging off and it would function the same. Or likewise with the smaller one in the bigger socket. If you didn't need those extra IO pins you could effectively drop it in as a substitute.  That also makes sense now as to why MCUs use ports rather than pins in the software.

If the pins went even on one side and odd on the other you could use the same code for bigger or smaller chips. But since pins aren't numbered like that, it wouldn't make sense to do it that way.

Then when I started getting naked AVR chips I had assumed they would be the same but they weren't. I was a bit disappointed but eventually came to understand that because smaller chips tended to have single pins that could be reconfigured to do multiple functions, that it was a decent trade-off.

[hans]

I work a lot with PICs, and when I see how the ports are laid out.. it's mostly 
When I open an AVR datasheet, it all makes sense.

If I want to connect stuff to the external parallel/memory bus of a PIC32 of a STM32 (too), it's all over the place. So is Ethernet RMII interface. It can be routed on 2 layers, but it takes up so many via's and layers, argh. 

A handy feature is reprogrammable peripherals on PIC24's, however.. it sometimes sounds like it's palliative if it cannot be used for large-pin interfaces.

[daqq]

It isn't designed to make you rage, usually its they way for a good reason, that you may not understand.
Look closely on the manufacturer's page for application notes, sample layouts, layout guides etc.
128 pins isn't that many, how many layers are you working with? If not 4layer already consider going to that.

I'm actually questioning if it was thought about at all. I mean, running the clock through the completely opposite side than where the target device is?

I already did the board layout once, now I just have to make a few changes and it's returning the horrible memories. The layout is on a 2 sided board.