licences are free. you get 30 days of the FULL tool. after that it falls back to a -base- tool . no support for the large devices, incremental compilation turned off , advanced optimizer turned off , ip cores stop working etc etc ... still perfectly usable for small to medium designs. ( when i say medium : you can still do a mulitliion gate design in a 484 pins bga without problems. just the 1500 ball devices are disabled. )
6 gigabytes. yes. becasue this tool supports ALL the devices they have. and the toolchain is enormous. these are not toys ... serious software has a serious footprint
file -> new project , follow the wizard.
file -> new sourcefile -> select verilog or vhdl ->start typing
on the risk of opening a huge can of worms : go for Verilog (most notably V2005 standard) and forget 'Very Hard Design Languge'.
There is simply too much 'overhead and typing involved in VHDL. Productivity in Verilog is an order of magnitude higher and for the FPGA or synthesizer it doesn't matter. You can always learn VHDL later. it's just a matter of syntax ( which involves a lot morekeystrokes to do the same in Verilog, simply becasue of the more 'strict' stuff. VHDL comes from the military, Verilog comes from people that want a tool to make designing chips easier. Here's the 'dirty laundry on VHDL' : VHDL or short for VHSIC HDL is a 'bolt-on' to HDL. The military commisioned a Hardware description language that could describe ANYTHING, whether mechanical , electrical , even a paper document could be described in it. think of it as a sort of XML. someone made a 'descritpio' of what a logic one and a logic zero is. and then went on describing the gates and other logical constructions using this language. All that stuff was slapped into a library ( two actually ) and that is how you can use the HDL to do logic work . without those libraries the HDL has no concept of logic high low , undefined or anything else ... Needless to say is that , using a generic language with bolt-ons requires a bit more work to get anything done. think of it as having to make a webpage using <html> tags. that is what coding in VHDL involves.
Verilog on the other hand was designed form the get-go to do logic and ONLY logic. you define logic and that's it. no need to add all the 'curly' bits.
VHDL has evolved ofver the years and some of the 'rough spots' have been removed but it is till bloody annoying not to be able to use generated signals back to read form without intermediaries , having the devine both a process and entitiy description and having the have for every block half a page of 'boilerplate bullshit' to get it to do anything. i don't like keyboard pounding, i want to write the logic.
anyway, all a matter of perspective. but to begin : verilog is syntactically easier and involves less keyboard pounding.
second : you are writing LOGIC , NOT CODE ! this is key difference between a sequenced system like a processor where one instruction happens after another. and a block of logic where every block executes at the tick of a clock.
Now, to make life easier you need to understand how a synthesizer works. this is something that 99.99% of the textbooks on VHDL and Verilog skip and it is absolutely important that you know this little bit as it makes life so much easier.
How do you translate a list of instructions ( which is our description of the logic ) into a parallel operating engine ? where is the 'magic' ?
the magic is simple.
you begin at the top where you find the definition of input and output and registers and you plunk those down.
and then you evaluat the first line of source. and you put down some wires and some gates, and then you read the next line and you cut some wires and throw in some more stuff and add some wires , and you keep doing that. and you grow TOWARDS the output. Meaning that :
a statement that is LATER on your page sits CLOSER to the output than e previous statement.
an example:
a counter with reset , preset , load , updown and enable. I'm using a 'hypothetical synthesis language without any 'curly' bits to make reading easier
signal names are CAPITAL
always @ CLOCK begin
if RESET then OUTPUT =0
else
if ENABLE then
if LOAD then OUTPUT = INPUT
else
if PRESET then OUTPUT = 9
else
if UPDOWN then OUTPUT = OUTPUT +1
else OUTPUT = OUTPUT -1
end if
end fi
end if
end if
end if
above is the 'traditional way of coding done by someone who has no idea how a synthesizer works. a pile of if-then-else spaghetti. if they tell you preset needs priority over clear, or clearing can only work when enable , but preset can work without being enabled you have to dig in and see what you need to chunk around and mess with things...
here is how you write this stuff 'scheduled'
always @ CLOCK begin
if ENABLE then begin
if UPDOWN then OUTPUT = OUTPUT +1
else OUTPUT = OUTPUT -1
end if
if LOAD then OUTPUT = INPUT
if PRESET then OUTPUT = 9
end begin
if RESET then OUTPUT =0
so how does this work ?
well i look at enable first. if the counter is not enabled , i do nothing
if a reset occurs : i wipe the counter.
if both were to happen at the same time : reset will take priority as it sits LOWER in the source file and thius CLOSER to the output
if ENABLE is true then we will avaluate UPDOWN and go up or down.
if LOAD is active then we will LOAD. since this statement sits closer to the output than the 'if UPDOWN' it takes priority. LOAD will have priority over the act of counting.
likewise PRESET has priority over the act of both LOAD and UPDOWN !
if someone telly ou that PRESEt has to work even when the counter is not ENABLED you simply cut that single line of code and move it outsde of the block that looks at ENABLE :
always @ CLOCK begin
if ENABLE then begin
if UPDOWN then OUTPUT = OUTPUT +1
else OUTPUT = OUTPUT -1
end if
if LOAD then OUTPUT = INPUT
end begin
if PRESET then OUTPUT = 9
if RESET then OUTPUT =0
done. PRESEt takes priority over whatever happens under control of ENABLE.
oh and preset needs priority over reset .. simply swap the last two lines. of and we wanted paralle load also outside of enable but with lowe rpriority than preset : you know the drill by now ...
you begin by giving the 'default' operation. when nothing else is in effect : do this...
unless ,,, blablab
unless blabla
unless blalbla
unless blabla ...
and so on :
if enabled then
if updown then +1 else -1
end if
unless load then out = in
unless preset then out = 9
unlesss reset then out =0
you are not going to find this in any textbook on Verilog for VHDL unless it is a textbook specifically written for SYNTHESIS. Most textbooks begin with the 'hello world' example. YOU CANNOT SYNTHESIZE THAT INTO LOGIC. you can simulate it , but you cannot drop this in an fpga or on silicon ! and that is boneheaded.
The technical name if Scheduled logic and it is partof the offcial Verilog AND VHDL standard. Any synthesizer out there needs to adhere to the rule that 'Logic shall be implemented in the order it is written.' simply because this is how the synthesizing process works. no escaping.
You can squash massive blocks of spagetti code to a few simple lines of code if you use the base principle of synthesis. It has an additional advantage : there are no undefined paths that lead to unpredicatbility , and there is no risk of latch inferral unless explicitly defined by you.
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