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Why not CMOS?

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Sal Ammoniac:

--- Quote from: Siwastaja on January 29, 2022, 05:29:10 pm ---Battery-backed SRAM is still a thing. Thanks to EEPROM and flash, not as much as it used to be, but still.
--- End quote ---

Another use of battery-backed RAM that's going the way of the dodo is on RAID disk controllers. These typically have several GB of RAM that's used as a cache. If the power fails, all of the dirty data still in the cache will not be written to the disk(s) and this can lead to data loss and filesystem corruption. The traditional solution was to put a battery (NiCad at first, then NiMH, and then Li) on the controller and use it keep the RAM powered until power was restored, after which the contents of cache would be written to the disk(s). When I was at LSI working on MegaRAID controllers, we typically sized the batteries to power the cache RAM over a three-day weekend (which we considered the worst case). These batteries were much bigger than a coin cell, and were a major headache for operators of big data centers because the batteries would have to be replaced every few years.

The solution to the battery replacement problem was to move to a new approach where the battery is replaced by a supercapacitor and FLASH. The supercap stores enough charge to power the board for around 30 seconds, which is enough time to write all of cache RAM to FLASH. After that the controller could stay powered down indefinitely without losing data. When power is eventually restored, the controller will write the contents of the FLASH to the disk(s).

Ian.M:
FRAM has its own issues - reads are destructive i.e. during or after every read cycle the on-chip controller *MUST* re-write the location to preserve the contents.   If power glitches during a read cycle or drops out of spec, you can expect data corruption.   e.g. https://www.eevblog.com/forum/projects/the-other-downside-to-fram/

David Hess:

--- Quote from: Sal Ammoniac on February 01, 2022, 04:30:46 pm ---The solution to the battery replacement problem was to move to a new approach where the battery is replaced by a supercapacitor and FLASH. The supercap stores enough charge to power the board for around 30 seconds, which is enough time to write all of cache RAM to FLASH. After that the controller could stay powered down indefinitely without losing data. When power is eventually restored, the controller will write the contents of the FLASH to the disk(s).
--- End quote ---

Before Flash memory existed we had SONOS which is what I used to replace the Dallas NVSRAMs in my Tektronix 2440 DSO.  It consists of a SRAM array in parallel with an EEPROM array and when power is lost, the entire SRAM array is copied into the EEPROM array in one step.

https://www.infineon.com/cms/en/product/memories/nvsram-non-volatile-sram/

David Hess:

--- Quote from: Ian.M on February 01, 2022, 04:31:29 pm ---FRAM has its own issues - reads are destructive i.e. during or after every read cycle the on-chip controller *MUST* re-write the location to preserve the contents.   If power glitches during a read cycle or drops out of spec, you can expect data corruption.   e.g. https://www.eevblog.com/forum/projects/the-other-downside-to-fram/
--- End quote ---

And FRAM requires a precharge cycle on every read so it is not always a direct replacement for JEDEC SRAM.

james_s:

--- Quote from: David Hess on February 01, 2022, 09:50:51 pm ---And FRAM requires a precharge cycle on every read so it is not always a direct replacement for JEDEC SRAM.

--- End quote ---

That's the issue I ran into. On a hardware level it is a direct replacement, but the software must be designed to meet the specific needs of FRAM.

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