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Why not CMOS?

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David Hess:

--- Quote from: Berni on February 06, 2022, 08:29:51 am ---Yeah for system that use a parallel interface SRAM chip are typically legacy ones that have the CPU sitting directly on the memory bus, using that bus as its main memory. Some CPUs can do the CS correctly some cant.
--- End quote ---

The JEDEC specifications for parallel access memory do not require toggling the chip select line between accesses.  Common FRAMs violate this so they are not JEDEC compliant.  This only became a problem when FRAM became available.


--- Quote ---Lots can likely be fooled into doing it by inserting an read instruction from somewhere else in memory as the data bus is typically the same number of bits as the native word size of the CPU.
--- End quote ---

Except for 8-bit processors, most of the legacy systems I have seen have a data bus width smaller than the CPU word length so routinely generate multiple memory cycles for the same access.


--- Quote ---That being said the FRAM chip i mentioned above does not need the CS to be toggled in order to work. You just get a speed penalty of running at about 1/3 full speed if you use like like SRAM. Even with that speed penalty this particular chip can run at 10MHz so still fast enough for most such legacy systems.
--- End quote ---

It has a 90 nanosecond worst case access time after an address change initiated pre-charge so should work fine in most legacy JEDEC SRAM replacement applications.

cortex_m0:

--- Quote from: dunkemhigh on February 06, 2022, 02:11:28 pm ---
--- Quote ---So as long as the firmware isn't treating a memory like that as a scratchpad
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This is the crux of it, and Tesla shows that even competent professionals get it wrong sometimes. Not to mention:

--- End quote ---

Tesla wouldn't be my first example for a company which puts quality first... as a long-time Chrysler owner, it must take serious ignorance of the matter to fall below Fiat-Chrysler in initial quality metrics.  :palm:

Tesla was using eMMC, which has several orders of magnitude fewer rated write cycles - perhaps 1000 to 5000 depending on the manufacturer and density. Doing one write per hour to eMMC is very different - under the same rules of estimation I used above, eMMC would last less than one year.

PlainName:
fair enough :)

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