### Author Topic: Will this signal destroy my uC pin?  (Read 2519 times)

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#### shapirus

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##### Re: Will this signal destroy my uC pin?
« Reply #50 on: May 22, 2024, 02:29:03 pm »
I have not answered, because i have no numbers yet. At least i want it not look so bad on the scope. It looks horrible with that zener alone.
Okay, as a starting point, will this be good enough?

Input: a 100 kHz triangle wave coming from a sig gen with 50 Ohms output impedance.

Traces: yellow is input signal before clamper, cyan is after it passes the clamper.
Math: yellow - cyan.
Probing: 10x oscilloscope probes, alligator clamp ground leads.

Peak voltage measurements are shown in the side window on the right.

1. 20 Vpp 0 V DC bias input:

2. 10 Vpp 0 V DC bias input:

3. 3.3 Vpp, +1.65 V DC bias input (so the signal is contained within the positive and negative clamping thresholds):

Schematic:

This is an illustration of the idea that I mentioned earlier, that is, to use fast diodes to clamp the input signal to power rails created specifically for such clamping.

The rails must be capable of sinking (positive) and sourcing (negative) enough current. The former is limited by DZ1, the latter is limited by R1 (decreasing R1 increases the negative clamping capability).

The voltage levels of such rails is chosen as Vr = Vc - Vf for the positive rail and Vr = Vc + Vf for the negative rail, where Vc is the desired clamping level and Vf is the forward voltage drop of the clamping diode(s).

In my example clamping starts at just about 3.3V and reaches almost 3.6V at +10V input, which is a bit too high: it's better to set the voltage of the positive clamping rail a bit lower.

Dependence of Vf on the current that's flowing through the diode determines how far from flat the clamped signal voltage will be. The higher the current, the higher the Vf. In other words, there is a certain voltage range in which the input signal is already distorted, but not yet fully clamped, and that is seen on the oscillograms as the output trace being non-flat where the input signal exceeds the clamping thresholds.

D1 and DZ1 are used in my example as a primitive way to set the clamping rail voltages. This is not power-efficient: a less wasteful way, where it is important, would be to use linear regulators or voltage follower op amps. Besides, as DZ1 starts to sink more clamped current, the voltage drop across it increases, thus further spoiling the flatness characteristic of the positive clamper. A beefy cap across the zener will help with that if the overload condition isn't lasting long.

Of course, this simulates pretty well, save for the effects of parasitic inductance and capacitance, which manifest themselves in hardware as phase shift and degradation of high frequency content between input and output.
« Last Edit: May 22, 2024, 02:34:40 pm by shapirus »

#### eTobey

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##### Re: Will this signal destroy my uC pin?
« Reply #51 on: May 22, 2024, 05:45:11 pm »
Okay, as a starting point, will this be good enough?

Yes it looks good, but thats with a rail, and i was wondering if it could be achieved without a rail.

I have something like this in my mind, what do you think about that? (see picture)
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#### shapirus

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##### Re: Will this signal destroy my uC pin?
« Reply #52 on: May 22, 2024, 07:02:40 pm »
I have something like this in my mind, what do you think about that? (see picture)
No it won't be clamping efficiently enough and it will distort your signal.

I strongly suggest that you learn how to run simulations (e.g. kicad+ngspice). It will remove a lot of guesswork and let you try various ideas.

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