I have a DC voltage with a high ripple current at 10 kHz which produces an audible noise from the MLCCs on the PCB. I can't change the frequency and I need to stick to MLCC class II capacitors for different reasons.
In this article:
https://www.newark.com/wcsstore/ExtendedSitesCatalogAssetStore/cms/asset/pdf/americas/common/nic-components/MLCC-Ringing-Singing-NSPH-SMT-FilmCapacitors-May2015.pdfthey say MLCCs mounted at the same place (e.g. same xy-coordinates) but on different sides of the PCB tend to cancel each other out. Is the same also true if the polarity of adjacent MLCCs would be reversed?
More specifically, assume I have different layouts where many MLCCs are placed close to each other, all connected to + and - of the DC-voltage:
Layout 1 Layout 2 Layout 3
[+-] [-+] [+-] [-+] [+-] [-+] [+-] [-+] [+-] [+-] [+-] [+-]
[-+] [+-] [-+] [+-] [+-] [-+] [+-] [-+] [-+] [-+] [-+] [-+]
[+-] [-+] [+-] [-+] [+-] [-+] [+-] [-+] [+-] [+-] [+-] [+-]
[-+] [+-] [-+] [+-] [+-] [-+] [+-] [-+] [-+] [-+] [-+] [-+]
Assume 1206 capacitors placed as close to each other as possible, e.g. the wavelength of the 10 kHz is large (34 mm) in comparison to the distance between MLCCs.
Layout 2 is obviously much easier to route compared to layout 1 and 3, but that's not relevant for the discussion here. I'd just like to know, if all else being equal, would any layout above produce less noise over the others due to cancellation av sound waves?