Author Topic: Adding ICT Test Points  (Read 1319 times)

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Offline stumpja

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Adding ICT Test Points
« on: September 18, 2020, 02:44:51 pm »
Hello Forum,

I've tried to find a procedure for adding ICT test points to a layout in CS in the documentation online, but I have not found anything yet. I need to create a TEST POINT, and place them with the following rules:

  • TP PAD >= 0.8mm
  • TP to TP >= 1.27mm (center to center)
  • TP to Assembly Outline (edge to edge)
  • TP to Board Outline >= 3mm (center to edge)

So I'm looking to understand multiple items here.

  • What's the best method of creating this test point?
  • What's the best method of placing the newly created test point?
  • How can I implement these rules for spacing into the DRC?

My primary PCB layout tool is Mentor PAD's Pro, and it's a bit convoluted creating the test point, but rules are easily managed in the DRC.

Thanks for your time!
 

Offline voltsandjolts

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Re: Adding ICT Test Points
« Reply #1 on: September 19, 2020, 05:06:45 pm »
A test point is just another component (with no BoM entry of course).

Create the footprint you want to use for the test point.
Then create a component (i.e. schematic symbol tied to that footprint), place them on schematic.
Then create rules in the PCB editor, just as you would for other components.
 

Offline T3sl4co1l

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    • Seven Transistor Labs
Re: Adding ICT Test Points
« Reply #2 on: September 20, 2020, 01:20:30 am »
Disclaimer, I use AD not CS, so I'm assuming common features here but I don't know for sure.

Any via or pad can be tagged as test point.  You set design rules to exclude undesirable kinds, like small or SMT pads, set the minimum distance between TPs, board edge, etc.

Adding test points may be as simple as assigning them to existing pads/vias.  If not enough match for the desired coverage, you'll have to add more.

You can add them as components.  Use a footprint with a single pin, THT or SMT, marked or no, and connect it on the schematic.  The nice part about this design method is, it's explicit on the schematic, what nets have test points added to them.  Bad part is it adds clutter, and is tedious and prone to error.

You can add them as free vias or pads.  Simply set the size as needed, and start placing them on nets.  Move into accessible locations, and there you go.

It's a good idea to plan for this during layout, since finding space for them in a complete design can be a nightmare.

If you are required to provide 100% test coverage, well, that's that.  Otherwise, but you may find it's desirable, or necessary, to skip small nets that are easily connected other ways.  Examples: nets tied by ferrite beads or jumper resistors; small value resistors for source termination or filtering; components in series combinations (for constructing a desired value, or for getting higher voltage or power rating); etc.  Certainly, prioritize important nets (signals and communications across the circuit).  Provide multiple TPs for power and ground.

Some special cases may be worth constructing with proper footprints.  For example, signal quality tests can be done with a coaxial scope probe footprint and component.  Or, a 2.45GHz antenna footprint can be tested by placing a U.FL connector nearby.  This can be done with minimal disturbance to the transmission line impedance, giving excellent signal quality.  (Use 0-ohm jumpers, or filter/matching parts, to connect to it for design testing.  This can be done on the other side of the filter/matching network too, to confirm correct tuning.  Leave them non-populated otherwise.  Or, use it as an assembly variant for an external antenna!)

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 


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