Via issue with polygon pour

[IanJ]

Hi all,

Here's a wee issue which caught me out today..........A via I had dropped from a FET didn't connect to the copper pour (green topside).

Limited space at edge of pcb but I thought a via smack in the middle of the pour will be fine.......but due to the relief connect being set to 4, conductor width 22mil, copper pour width 26.7mil at the via it somehow caused the via to completely disconnect from the pour. I think that the calculation is done on the via size 30mils (greater than 26.7?) and thus it decided "no fit".

Moving the via slightly to the side and repouring it's ok again, but I would have thought CS would make an attempt to attach even partially.

Ian.

Issue:


Fixed:

[voltsandjolts]

Yeh, not great, but at least the design rule check would have caught it if you hadn't spotted it first.
I use solid connect on vias.

[rs20]

That via is in a worse place now. Why not just draw a trace? That seems easier that tricking the software into adding the connection for you.

[IanJ]

That via is in a worse place now. Why not just draw a trace? That seems easier that tricking the software into adding the connection for you.

Just demo'ing what to do to fix it minimum.

Ian.

[IanJ]

Yeh, not great, but at least the design rule check would have caught it if you hadn't spotted it first.
I use solid connect on vias.

I would to, but there are some battery connectors which would be much harder to manual solder with solid versus 4 connects.
I did look into finding out how to mix both on the pcb but not easy, I wish there was a simple override in the via properties to select solid, 2 or 4 way.

Ian.

[voltsandjolts]

You can setup rules such that vias are direct (solid) connect and everything else is heat relief connect.
For example: