RISC-V SoftCPU Contest

[FrankBuss]

There is a contest for writing a RISC-V implementation for FPGAs: https://riscv.org/2018contest/
1st prize is USD 6,000. But the rules are a bit fuzzy, like how will they weight logic elements and block RAM usage to compare different designs for the "smallest implementation" category? It wouldn't make sense to say a design which needs 1 kBit RAM and 5 k logic elements is "smaller" than a design which needs 50 kBit RAM and 1 k logic elements. I already wrote them an eMail with this question, but no answer so far.

Another problem is the tight deadline: Nov. 26, 2018. Just reading and understanding the specification of the RISC-V, setting up all the software, emulators, and playing a bit with it might need already a few weeks, if you don't do this full time, or if you don't know it already and have the emulator running.

On the plus side you can get a free FPGA devkit, if you promise to submit a contest entry.

[SiliconWizard]

"    Can I use VHDL?
    Your design must simulate in Verilator. Verilator does not support VHDL.
"

Shame.
 

[abraxa]

"Entries have to be submitted in the form of repositories on github.com with a clearly stated BSD-style license (the Apache 2.0 license is preferred)"

Ha. Ha. Ha. BSD-style. Apache 2.0 preferred. Why would they state that? Oh, I don't know... maybe because of this clause?

"[...] each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable copyright license to reproduce, prepare Derivative Works of, publicly display, publicly perform, sublicense, and distribute the Work and such Derivative Works in Source or Object form."

In other words: they can use the stuff in their products without paying you a single cent in royalties or license fees! They can even SUBLICENSE your work and charge money for it. Now if I was one of the companies, I'd say that's a bargain for $13000 and a few dev boards (that are pretty much free to the manufacturer anyway). Even then, the $13000 come out of the budget of the marketing department since this is a PR event to "promote" the RISC-V platform. Now that's a good deal for them if I ever saw one.

I'd give them a big FUCK YOU if I could and definitely not participate.

[FrankBuss]

"Entries have to be submitted in the form of repositories on github.com with a clearly stated BSD-style license (the Apache 2.0 license is preferred)"

Ha. Ha. Ha. BSD-style. Apache 2.0 preferred. Why would they state that? Oh, I don't know... maybe because of this clause?

"[...] each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable copyright license to reproduce, prepare Derivative Works of, publicly display, publicly perform, sublicense, and distribute the Work and such Derivative Works in Source or Object form."

Yes, this is standard for BSD-style licenses, and I like it, because this means I can use other designs as well in my commercial products. This is the concept of open source: give and take. Usually I release my stuff as open source, too, if it is my own project, or if my client allows it.

And no problem if they want to promote the RISC-V. It is a win-win deal: they get some PR and you get some money if you win. And you can still use and sell your core as well, even when they are selling it. Of course, there are already a few very good open source FPGA implementations of the RISC-V available, will be difficult.

Regarding the Verilog requirement: You could use something like Chisel, or develop it in VHDL, then translate it to Verilog. I've tested a few products, free and commercial, and this was the best so far:

http://www.syncad.com/verilog_vhdl_translator.htm

The price is ridiculously high ($250 per day), but you can get a free one-day evaluation license. Sufficient to convert the project, once it is working in VHDL.

Meanwhile I finished writing a simple C emulator, optimized for the RV32I architecture, based on a more complex emulator, which passes all compliance tests:

https://gist.github.com/FrankBuss/c974e59826d33e21d7cad54491ab50e8

Now I just need to convert this to Verilog (and setup the FPGA projects, add the boot-code, UART etc.). Or find a small core which has a C compiler and just compile it, which I think is allowed by the contest rules. They don't say it is forbidden that you use a 6502 core and CC65 to compile the C to microcode to emulate the RISC-V core

[a59d1]

"Entries have to be submitted in the form of repositories on github.com with a clearly stated BSD-style license (the Apache 2.0 license is preferred)"

Ha. Ha. Ha. BSD-style. Apache 2.0 preferred. Why would they state that? Oh, I don't know... maybe because of this clause?

"[...] each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable copyright license to reproduce, prepare Derivative Works of, publicly display, publicly perform, sublicense, and distribute the Work and such Derivative Works in Source or Object form."

In other words: they can use the stuff in their products without paying you a single cent in royalties or license fees! They can even SUBLICENSE your work and charge money for it. Now if I was one of the companies, I'd say that's a bargain for $13000 and a few dev boards (that are pretty much free to the manufacturer anyway). Even then, the $13000 come out of the budget of the marketing department since this is a PR event to "promote" the RISC-V platform. Now that's a good deal for them if I ever saw one.

I'd give them a big FUCK YOU if I could and definitely not participate.

The competition doesn't seem super insane to me. RISCV just wants to promote the platform; what's wrong with them paying an engineer $6k for a few weeks of work? It's about market rate, no?

If you want to keep your RISCV design to yourself, nobody will stop you from licensing it however you like. You just can't submit it to the ccompetition and probably nobody will buy it because RISCV is open-source.