openvizsla......... still......

[mrflibble]

Oh yeah, do you happen to know if you can do the following in a non-painful way:

Generate an array of modules, and then generate constraints for those as well. Generate constraints, purely based on source file I mean. Mostly LOC's, but sometimes moderately creative ROUTE constraints as well. I have a solution for that, but sometimes it's not very pretty (nor maintainable).

In that regard VHDL is a bit nicer, since there you CAN write attributes during synthesis. In verilog if you want it on source level you can only use comment style. And comment style ... you cannot dynamically emit new comments that get parsed during synthesis.  So if you want the full feature set you end up using a (perl) script to update an external UCF file. And then comment the hell out of your source file so you still know what you're doing here.

And just to be clear, in all the above I mean verilog-2001. Not SystemVerilog or even verilog-2005. Since verilog-2001 is basically what you have to deal with if you use ISE.

[marcan]

How is it in handling say 50% code written in pure verilog, and 50% code handled by migen? Ditto for mixed verilog + vhdl. Because ideally you'd want to be able to mix & match. Say you want to use a PLL core from coregen, plus have some old already proven modules.

You can instantiate arbitrary Verilog modules (and VHDL too I think) easily. I almost did that with an external .v for our PLL, but I ended up instantiating the primitive straight from migen (here).

Mmmh, might be interesting to just give it a try. Any good examples to be found besides the stuff provided with the download? As in, any magic places on the internet to find extra resources for it? Because that might be one other issue with using it, tiny userbase.

Well, yeah, the documentation is... not comprehensive and somewhat outdated. I definitely wouldn't suggest it if you can't deal with that . But I'm happy to work things out myself considering the good parts of migen that I've seen so far. Anyway, reasonable examples are probably our stuff and the canonical project that migen was developed for, milkymist-ng. I hope it matures a bit and becomes better documented with time.

Generate an array of modules, and then generate constraints for those as well. Generate constraints, purely based on source file I mean. Mostly LOC's, but sometimes moderately creative ROUTE constraints as well. I have a solution for that, but sometimes it's not very pretty (nor maintainable).

I'm not sure if there's a built-in way to fire off constraints to the UCF file from a module, but it should be trivial to implement yourself; just keep an array of modules that need constraints and then read it off in the platform's do_finalize method to generate the UCF. You could even use the module walking stuff in migen to make it automagic (e.g. for every module instance in use, check for a magic property/method and generate UCF from that).

I do some trivial UCF generation (clock period constraints) in ov3 here.

The beauty is that since it's python, it's really hard to come up with something that you *can't* do (migen may or may not do it off the shelf, but you can always implement it yourself in whatever way you deem reasonable).

[MacAttak]

This side discussion is really interesting, but would probably be better if it was relocated to the FPGA section. Most people wouldn't think to click on an overdue crowdfunded project to find migen discussion

[mrflibble]

Yeah, sorry about the off topic bits. I'll ask if an admin can move it. Maybe to the Open-source software for Verilog synthesis thread, since migen is precisely that.

Update: okay, request sent...

[marcan]

Yeah, sorry about the off topic bits. I'll ask if an admin can move it. Maybe to the Open-source software for Verilog synthesis thread, since migen is precisely that.

Update: okay, request sent...

Not quite - migen generates Verilog, so it doesn't synthesize anything. It's a higher-level tool. But yes, this discussion should be moved elsewhere...

[desowin]

Archeology time! 

I have received OpenVizsla PCB. Now I need to order components and get it soldered.  Too bad mouser doesn't have the main FPGA (XC6SLX9-3TQG144C) available (I don't think > 49 USD for shipping from DigiKey is good deal...) so I'll have to order most parts from Mouser and the FPGA from some other (local) retailer.

[firewalker]

You had pledged for a bare bone PCB?

Alexander.

[mrflibble]

Or you could just order everything from digikey, and pad the order to amount required for free shipping with fun dev-kits and those-passives-you always-run-out-of.

[krivx]

Are they shipping orders or did you have a PCB fabbed? I don't know how to follow this project anymore. There hasn't been activity on github in a couple of months.

[desowin]

You had pledged for a bare bone PCB?

Yes.

Are they shipping orders or did you have a PCB fabbed? I don't know how to follow this project anymore. There hasn't been activity on github in a couple of months.

I am 50 USD backer and received the reward (bare bone PCB and 50 USD off coupon code for fully assembled unit). There is some limited activity on the OpenVizsla backers mailing list. AFAIK the higher tier pledges will be sent later (fully assembled units) and after that the DIY kits (PCB + all components) will be sent (from the leftover parts after assembly).

[FrankT]

Woot!  Mine arrived today.

Just need to find time to play with it now.

[firewalker]

Lots of logos!

Test it and tell us if it is what it should be.

Alexander.

[John_ITIC]

I've been through the same thing Bushing and his team went through since, I too, created my own USB Protocol Analyzer (as well as one for PCI Express). They for sure had their work cut out for them.

My own 1480A USB 2.0 LS/FS/HS design was created between 2005 and 2009 in my evening and weekend spare time. Essentially, it was a massive effort required despite 20+ years of professional EE and CS experience. I found that there is a reason these things cost thousands of dollars....

/John.

[Smokey]

Looking through osmocom stuff tonight I saw a familiar name....

So the guy Bushing apparently passed away in 2016: https://fail0verflow.com/blog/2016/ben/
And the project sorta found a home at osmocom: https://osmocom.org/projects/openvizsla